( ESNUG 525 Item 1 ) -------------------------------------------- [05/28/13]
Subject: Questions for Joe Sawicki, GM of Design-to-Silicon at Mentor
Cooley's DAC 2013 Troublemaker's Panel
Date/Time: Monday, June 3, 3:00-4:00 pm
Location: Ballroom G, Austin Convention Center
IF YOU WANT TO ATTEND THIS DAC PANEL, SIGN-UP HERE.
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QUESTIONS FOR JOE SAWICKI
I'd like to hear a quick status on the 5 Mentor products:
- what's up with Calibre and its deriavtives?
- what's up with Olympus-SoC?
- what up with Mentor test and scan?
- what's up with Veloce 2?
- what's up with MENT PCB vs. Cadence?
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Sawicki -
What's it like to be sued by Aart's lawyers about EVE a full 5 days
before Synopsys announced it bought EVE?
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Do you think Carl Icahn regrets ever seeing the letters E.D.A.?
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Why is Calibre using the same SKILL interface to Virtuoso ADE that
BDA is? Why does BDA get sued for this, but not Mentor?
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Did MENT really get kicked out of the Cadence Connections program?
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Why does Mentor contractually require customers not to allow Calibre
SVRF to be used with other DRC tools?
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Now that Cadence PVS works at comparable speed with Calibre do you
see some of your market share going to Cadence?
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Some claim 20 nm full custom requires interactive DRC feedback
using Calibre RealTime or Synopsys ICV. Is that true? Does it
matter if the feedback is based on the actual signoff rule deck?
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To Mr. Sawicki:
Can you give me a compelling reason to switch to Pyxis over Virtuoso?
Virtuoso is easily 5 years ahead of what Pyxis has to offer.
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Is IC Station trying to gain some full custom market share now that
Laker and Ciranova are part of Synopsys?
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Joe (Ment) -
Your PNR vacuum still remains, when would you fill it - if ever?
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Wally and Greg tell Wall St. that Veloce sales is pulling ahead of
Palladium sales. Is it true? Why is Veloce getting these wins?
Where is Cadence messing up in emulation?
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Sawicki:
We are a few years into UVM, and the tides of frustration appear
to be rising. What happens next?
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Why did you "gobble up" Axiom? For debug? If yes, when will
users see the benefit?
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Is raising up from RTL to TLM really where designers want to go,
or is this just a marketing push for new tool sales categories?
Name names and give real data of anyone who's gone TLM.
Have any productivity or TTM gains actually been proven?
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Synopsys and Cadence do these massive "all-you-can-eat" total flow
deals with Intel, Freescale, etc. How does Mentor compete?
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When Synopsys closes access to Milkyway and Cadence restricts its
interface to Virtuoso, how can Mentor survive? Isn't this what
the FTC would call a "tie-in" sales practice? Why doesn't the
Federal government step in on this?
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What's going to break after 14 nm? Will we need triple patterning,
source mask optimization, radical OPC, what?
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You now need 100's of PCs to get reasonable turnaround time for
place and route (ICC, Olympus, Encounter), DRC (Calibre, ICV, PVS),
litho checking (LFD,LPA) and timing (PrimeTime). Is this becoming
a barrier to IC startups? Other than you trying to sell us space
on your cloud (no, thank you) what other ideas do you have?
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10 nm will be hugely expensive! What chips will justify it? Why
not do 3D-IC instead?
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At 14 nm, GlobalFoundries and ST want FDSOI. TSMC wants FinFET.
Who's going to win and why? What's Mentor betting on?
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Joe Sawicki: How important ist he IC/Packaging/PCB Codesign?
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Why did IP flop at Mentor?
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Is Wally bidding on Atoptech? Why or why not?
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