( ESNUG 521 Item 2 ) -------------------------------------------- [03/28/13]
Subject: 57 engineers "colorfully" react to Drako IP Reuse 2.0 proposal
NO LONGER 2ND CLASS: Along with the usual mix of engineers arguing about
the specific points brought up in Dean Drako's survey, the fact that he
gave very public recognition that VERIFICATION is the neglected half of
IP Reuse 2.0 brought out a swarm of agreeing Verification Engineers.
P.S. And it was also interesting to see the point-counterpoint readers
were making about OTHER ASPECTS of this IP Reuse 2.0 proposal.
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Like.
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Thanks, John. Our loudmouthed SW guy has spent half of today
walking into our cubes pulling up this letter and then pointing
at the screen yelling "SEE??? SEE?? SEE!!!??". He's not going
to shut up for weeks on this, I can tell.
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Good
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Now all I have to do is to convince manangment that this was
their idea in the first place and we might actually do it. :)
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Thank you! This is very interesting.
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If this was Facebook, I'd "LIKE" it.
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I wish I had the political capital to make such changes in our
company. No one listens to verification engineers like me.
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Good stuff.
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Well, duh! Of course, reuse should include both design AND
VERIFICATION reuse! Like this is news???
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Someone else "big" finally recognises verification counts?
It's about time!
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Verification is no longer second class in the design house.
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It's good to hear someone say verification matters. Any idiot
can slap down a few thousand gates and call it a design. But
it's not a design until it's been verified.
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Good.
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Dean's Reuse 2.0 kicked off some much needed discussions in our
company. Thanks.
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Infrastructure? Yawn.
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63% say EDA verification tools need the most improvement.
Tell me something I don't already know. Should be 100%.
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> "For efficient IP reuse across the enterprise, your company must
> master BOTH the design AND the verification aspects."
>
> - from http://www.deepchip.com/items/0520-01.html
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Dean forgot to add "and also the reuse of product specification
content!". These SoCs have 10 K+ pages of specs nowadays...
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Our normal Friday morning group status beating was pre-empted by our
pointy-haired bosses telling us we have to now drop everything for
this proposal that will suck up our time for little, if any, real
savings. Tell Drako we send a sarcastic "thanks" for the added work.
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Goldmine of information here. Thanks!!
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Does the IC Manage guy realise 99% of what he proposed can be done
with any worthwhile DM SW suite? IC Manage has no lock on this?
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Dean's not very creative. My company has been doing for years what
he's now proposing. Appears he just copied our ideas.
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GOOD
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CC: my boss and my group. We should do this.
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Tell Dean thank you for his post. We're using it as a first draft
spec for our IT Department to implement. We may or may not
contact him about GDP, but he should get credit for initiating
this change at our company.
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IC Manage is in the wrong business. Instead of SW sales, they
should go into organizational consulting. The major gains we'd
see from the Reuse 2.0 proposal almost all come from company-wide
behavioral changes; not from the SW package he's offering.
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If only I could get Dean to whisper this into my VP's ear.
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I'm happy using ClioSoft with ADE. Have used my own design lib
for years. Don't see what all this fuss is about.
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One of our first year engineers emailed Dean's 10 best practices
to our developement group. You could hear laughter from the
cubicals off and on all afternoon. These kids have no idea how
corporate politics work.
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Yes!
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Don't mean to pee on his parade... Any experienced programmer
will tell you Dean's so-called Reuse 2.0 "proposal" is all
common sense ideas swiped from the SW development world.
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> 8. Set up and utilize a checklist-driven flow during IP development
>
> - from http://www.deepchip.com/items/0520-04.html
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Liked the checklist idea. Simple and effective. Thanks.
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Checklists good!
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Checklists are common sense yet so difficult to teach some bosses.
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> The checklist idea is not to restrict the use of the IP but rather
> to encourage certain steps being taken when it's stored or used...
> Checklist items span both design progress -- such as LVS/DRC clean
> or variation-clean -- and verification progress.
>
> - from http://www.deepchip.com/items/0520-03.html
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AS I SAID BEFORE TO YOUR RTDA QUESTION, PLEASE DO NOT PUBLISH
CRAP LIKE THIS!!!
Please don't give my idiot CAD guys ideas about their taking
control of my design flow. These do-nothing morons don't have
the first clue what it really takes to tape-out a real chip
and I don't have 100 years to teach them.
PLEASE STOP GIVING THEM THESE IDEAS, JOHN. IT'S NOT HELPING.
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Let our IT clowns control our design flows? What fresh horror
is this?????
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> The 260 respondents whose companies had implemented significant
> IP reuse dependency management systems and processes stated:
>
> 1. Average 31% reduction in engineering resources needed.
>
> 2. Average 30% faster time-to-market.
>
> - from http://www.deepchip.com/items/0520-05.html
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Are these stats on design reuse vs. no design reuse? Or current
design reuse vs. IP Reuse 2.0 design reuse?
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Ask Drako to name the companies today doing Reuse 2.0.
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Good data. Thanks.
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Dean's claim (31% less staff, 30% faster TAT) in hard terms:
NO IP REUSE WITH IP REUSE
staff: 3 design engineers 2 design engineers
9 verification engineers 6 verification engineers
3 layout guys 2 layout guys
1 CAD guy 1 CAD guy
time: 10 months to tape-out 7 months to tape-out
total: 160 man-months 77 man-months
I think this data on the impact of design reuse is conservative.
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> 5. Encapsulate design AND verification data with IP for reuse.
>
> - from http://www.deepchip.com/items/0520-04.html
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It's a myth of looking in a library of in-house IP. We only do a
few key differentiating pieces of in-house IP for reuse. Costs are
prohibative to make all prior designs reusable.
Also disagree with the idea of the in-house IP developers adding
their test suite that goes with the IP in the archive.
On purpose, even though both Synopsys and Cadence dislikes it
because it splits their sale, we buy hard DesignWare IP from
Synopsys and separate Verification IP (VIP) from Cadence just
to have two unrelated teams make and verify it.
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In-house IP reuse isn't all that it's being touted to be.
Years ago Aart once said during the early DesignWare days that it
took 3X the original effort to make a design reusable. I doubt
most organizations are willing to go back to do this with their
prior IP. Too much re-engineering time (and money) for no glory.
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Reuse 2.0 doesn't work for async designs. Timing is too messy.
Also doesn't work for legacy designs. People who know guts of
the original designs are long gone.
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> Non-memory SoC and IC design content
>
> Internal IP: ###################### 44%
> 3rd Party IP: ############ 24%
> New Design Content: ################ 32%
>
> - from http://www.deepchip.com/items/0520-01.html
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What does "design content" mean? 44% + 24% of it is IP. Is that
silicon area? NRE dollars spent? Lines of code? Something else?
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Do you know the average split between memory and non-memory in
most designs today? What percentage mem is L2 vs. non-L2?
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Were these control-intensive or data-intensive designs?
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At what process node? 32/28/20 nm? At what average clock?
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How would an ARM core count in this survey if it was modified?
As reused IP or as "new" design?
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> Average Time Spent On Verification Tasks
>
> Developing Testbenches: ############# 26%
> Writing/Running Tests: ############# 26%
> Identifying Bugs: ############ 25%
> Managing Bug Dependencies: ######## 17%
> other: ### 6%
>
> - from http://www.deepchip.com/items/0520-02.html
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Liked your verification time study, but was confused on the
difference between your "Developing Testbenches" (26%) and
your "Writing/Running Tests". To me they're the same thing.
Combined they take up 1/2 my time.
I also agree 20% of my time is chasing bug dependencies.
Good data.
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> Tier 2:
>
> 6. Lack of processes and/or designer participation (35%)
>
> - from http://www.deepchip.com/items/0520-02.html
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TIER 2?
This is WRONG. This is a TIER 1 problem. Solve lack of
processes plus get designer buy-in and everything else
will fall into place.
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> Instead engineering groups need to do continuous design.
> Multiple designs are underway at any one time.
>
> - from http://www.deepchip.com/items/0520-01.html
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Continuous Design reminds me of the old saying: "Sometimes
you have to shoot the engineers and make the damn thing."
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My wife says as a husband I'm a continuous fixer upper.
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Isn't Continuous Design "kaizen", a Japanese management idea
from back in the 1980's that means "continuous improvement"?
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Blind survey? Why not survey sight-enabled engineers, too? :)
(Good data BTW.)
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Wish we could do this but we're mid project. Too big a hit
for us to take right now.
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Q: What's the difference between Reuse 2.0 and Synopsys Lynx?
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Ha! We're lucky if our Indian design group meets 70% of our
design spec; much less the wild idea of them creating portable,
fully documented, reusable testbenches for their blocks. Ha!
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Is this by the Dean Drako of Barracuda Networks fame? Or is this
a different guy by the same name?
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