Arteris CEO corrects Jim Hogan's commercial NoC comparison chart

( ESNUG 516 Item 5 ) -------------------------------------------- [12/13/12]

Subject: Arteris CEO corrects Jim Hogan's commercial NoC comparison chart

> Below is my grid comparing current commercial Network-on-Chip (NoC) IP.
> In it, I compare NoC IP from Sonics, Arteris and ARM, according to
> metrics in my prior "commercial NoCs evaluation metrics" section.
>
>     - Jim Hogan
>       Vista Ventures, LLC                        Los Gatos, CA
>       http://www.deepchip.com/posts/0511.html


From: [ Charlie Janac of Arteris ]

Hi, John,

I saw Jim Hogan's table comparing our Arteris FlexNoC vs. his Sonics SGN vs.
ARM's NIC 400.  While I can not presume to speak for ARM, I would like to
correct some of the errors Jim had made about Arteris in his original table.

My corrections are in blue below:

Company	Sonics	Arteris (Janac)	Arteris (Hogan)	ARM
Product	Sonics SGN	FlexNoC	FlexNoC	NIC 400
Performance, Power, Area	>1 GHz performance, power management signaling and fully clock gated, efficient gate count.	1 Ghz+ capability. Fastest customer silicon in production is 800 Mhz in 40n m HP process. 0.7 mW idle power for 1M gate NoC instance. 100's of features for power conservation.	533 MHz, Power Compiler based clock gating, and good area at lower frequencies.	533 MHz, Power Compiler based clock gating, good area.
Scalable-Adaptable	Scalable architecture supports a large number of number of cores (only verification limit). Fabric speed scales for narrow and fast configurations or wide configurations. Architecture supports socket based (AMBA and custom) interfaces separating cores from fabric for flexibility with chip modifications. Existing Interfaces with other fabric IP components for optimal topology configuration.	Unlimited number of IPs. Proven in customer SoC with 150 top-level IPs. Multi-NoC capability. Supports the AMBA protocol portfolio and 12 other protocols. Scalable to small designs and blocks as well as large designs.	Flexible multiplexer/de-multiplexer based switches. Modular register slice anywhere in the network. Network interface unit	Bus matrix style network (not packetized). Multi-layer design. AMBA interface support.
Quality of Service (QoS)	Initiator-based QoS, with credit-based flow control. Non-blocking.	Distributed QoS. Non-blocking. Multiple level QoS including proprietary pressure mechanism	Initiator-based QoS.	Initiator-based QoS.
Virtual Channels	Yes, native virtual channels, with up to 16 channels per link.	For gate count conservation Arteris does not use virtual channels. Virtual channels are too inefficient and wasteful.	No.	Yes, optional virtual channel component.
Layout Friendly	Multiple clock schemes supported to allow crossings anywhere in network. Virtual Channels to preserve the architect intent, when modifying network to match layout.	Arteris uses half the wires of a hybrid bus. Distributed NoC element architecture eliminates congestion points. Physical aware NoC considers physical constraints during architecture development.	Span distance with pipe point; adds gates and latency.	Split bus matrix. Network configured by user.
Power Domain Partitioning	Unlimited number of power and clock domains. Flexible domain crossing can be placed anywhere in the network. Fast hardware controlled domain for power sequencing.	Arteris domain crossings are placed inside the interconnect wherever it is most efficient.	Domain crossing at edge of network.	Component based, configured by user.
Memory optimization	Non-blocking fabric enabled by virtual channels combined with credit-based quality of service algorithms. Optional DRAM scheduler can be added to the network.	Optional memory scheduler IP available. QoS is distributed. Memory interleaver for multi-channel memories. Separate request/response links make NoC non-blocking by definition.	Initiator-based QoS. Optional memory scheduler IP available.	Initiator-based QoS with optional components like virtual channels to help with blocking.
Cache coherency	ACE-Lite support.	Has both full ACE protocol and ACE-Lite support. Interface to ARM CCI-400 coherent interconnect in silicon	ACE-Lite support.	ACE-Lite and CCI-400 external IP for full coherency.
System Verification	Automatic UVM based verification of configured network (includes Synopsys VIP).	Uses Synopsys, Cadence, Mentor and internal VIPs. Arteris FlexVerifier tool handles unlimited number of switches.	Proprietary verification scheme.	AXI Protocol compliant.
Latency	Native AXI/OCP sockets for best gate count/timing closure. Fabric configurations allow zero cycle latency.	Proprietary Zero Latency NoC for latency sensitive connections. Wormhole routing. Fewer gates. Low latency Network Interface Units (NIUs)	Not mentioned in original analysis	Not mentioned in original analysis
Silicon-Proven	2 billion units shipped from 200+ designs, without any silicon failures, based on patented verification methodology	110 designs and 45 tapeouts at 46 customers. Majority of mobility chips use Arteris FlexNoC. 100M units in 2012.	Not mentioned in original analysis	(Try to find a chip on Earth that doesn't have at least one ARM core in it.)
Security	Multi-level firewall (superset of TrustZone support).	TrustZone support and customizable security IPs for enhanced security support.	TrustZone support.	TrustZone support.
Chip- Package- Board Interposer Support	Wide I/O enabled with native fine grained multichannel memory capabilities.	Wide I/O enabled with optional multichannel memory.	Wide I/O enabled with optional multichannel memory.	No.


In closing, I'd like to highlight that our Arteris FlexNoC has been used in
at least 120 SoC designs -- mostly the mobility/consumer space -- and has
gone through 9 revs (because so many customers have asked us to add certain
features and enhancements.)

Our FlexNoC is a mature On-Chip Communication Network, which is why Samsung,
Qualcomm, and Texas Instruments use us for their key designs.

    - Charlie Janac
      Arteris, Inc.                              Sunnyvale, CA

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