( ESNUG 515 Item 7 ) -------------------------------------------- [11/29/12]
From: [ Jim Hogan of Vista Ventures LLC ]
Subject: Hogan outlines the current players for the Custom 2.0 retooling
Hi, John,
Now that I've outlined the drivers and requirements in each of the four
quadrants of the Custom 2.0 retooling:
Figure 2: Custom 2.0 Key Aspects
here's my take on the current players in each of these four quadrants.
SPICE SIMULATION PLAYERS
The SPICE simulation and analysis market continues to be fragmented with
different players and products that are strong in distinctly different
segments (See fig 11).
Figure 11: Custom 2.0 verification market vendors
The various applications discussed earlier, custom digital, memory, clock and
I/O, mixed signal, analog, RF, microwave, MEMS, and EM, can each require
different technology approaches and environments. Best-in-class simulators
win over having one simulator for all areas. Further, engineers can be
reluctant to change from a simulator that works.
Ansys/Apache and National Instruments have the currency to enter the circuit
simulation market, and an acquisition such as Berkeley DA (BDA) would grant
them immediate standing, as BDA has evolved to be going concern with a base
of over 100 customers.
In addition, the ElectroMagnetic (EM) players see opportunities in the
semiconductor market with increased used of 3D packaging and ICs. AWR
recently introduced EM to their microwave design environment, joining
Ansys (Apache), Agilent, and Nimbic in EM with their AXIEM product.
With Synopsys acquiring Magma in February 2012, Aart gained an initial
monopoly in the custom digital and memory/std cell library markets.
However, the disappearance of Magma as the second-source SPICE vendor in the
custom digital and memory/std cell library markets immediately created
a vacuum -- and a real opportunity for Cadence and Berkeley DA to build
market share as replacements, leveraging their adjacent positions in
analog/mixed signal/RF market, as well as their positions in custom digital
and memory characterization.
Both Cadence and BDA have already added new offerings and gained initial
penetration. Cadence extended its current offering with XPS simulation,
and BDA expanded its capacity, accuracy and precision to capture the
requirements for memory at 20 nm and below.
Synopsys' resources have now shifted from fighting Magma in its home turf,
to supporting a slew of acquisitions such as SpringSoft and Ciranova,
expanding into the analog/mixed-signal markets to compete against the
Virtuoso platform.
Over the next three years, we will see some significant realignment of
customers and their SPICE simulators as their time-based licensing
agreements are renewed.
VARIATION ANALYSIS PLAYERS
The established variation analysis players are Cadence, Solido, and MunEDA.
Solido provides interactive variation analysis, and MunEDA's products were
built on more automated optimization approach. Cadence includes core
variation analysis as part of their ADE environment.
Figure 12 shows the design environment vendors. Design environments are
used to setup, efficiently run and visualize the results of simulations
required to design and verify custom ICs.
Figure 12: Custom 2.0 Design Environment Market Vendors
In addition to Synopsys, which provides a command-line interface, and
Cadence with a GUI environment, we have Solido Design and MunEDA. Both
vendors are SPICE neutral, providing integrated environments with all
the SPICE simulator vendors and driving SPICE simulator usage across
designer compute farms. For the memory and custom digital markets Solido
and MunEDA run command-line batch modes with netlist input; for the
Analog/Mixed Signal and RF markets, they offer GUI interfaces.
Some environment vendors, such as Solido, manage the enormous amount of
variation data by including variation analysis in their environments.
Solido furthermore reduces the number of SPICE simulations by knowing what
to simulate rather than doing brute force analysis, because simulating for
variation raises the requirement for SPICE simulation runs.
Since its acquisition of SpringSoft earlier this year, Synopsys must try to
converge on a single simulation base for FineSim and HSIM.
Additionally, I believe Aart still needs to resolve whether he goes with
Custom Designer from Synopsys, Laker from SpringSoft, or a combination of
the two. Laker has a larger market share, but Custom Designer is a more
open environment and used extensively in Synopsys' IP business.
My guess is the market won't let Laker disappear anytime soon. Also, within
the broader custom design market, in my opinion, the memory and custom
digital designers need a lighter weight environment than do the analog
designers. Thus for the first time, we see several environments starting to
emerge to serve those specific market segments.
3D TRANSISTOR PLAYERS
We need to contrast the 3D transistors from Intel, IBM and TSMC at the
various process nodes - they are very different. Intel is being very quiet
about how they get the process to work for them; they are not sharing
information with the equipment suppliers. Companies like TSMC now must
essentially go it alone without the benefit of Intel's R&D and the pass
through to followers such as TSMC and Samsung.
Another promising area is the virtualization of the semiconductor process
architecture and integration. Coventor's SEMulator is an interesting
product that does this virtualization.
IP REUSE DEPENDENCY MANAGEMENT PLAYERS
The established players in IP reuse dependency management are IC Manage and
Dassault. Some of the other players with technology in this area are
ClioSoft and Methodics.
CONCLUSION
This Custom 2.0 retooling has already begun.
My goal is to set the context and framework for it. I'd like to encourage
any DeepChip readers, whether they are EDA users or EDA vendors, to help
flush this out further -- or let me know where they agree or disagree.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
Editor's Note: As mentioned earlier, Jim's on the Solido board. - John
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Related Articles
Hogan on the early days of Custom 1.0 and Cadence Analog Artist
Key aspects, market drivers for the present Custom 2.0 retooling
Atomic scaling problems, Variation, and the Custom 2.0 retooling
Custom 2.0 means that SPICE runs must BOTH be fast AND accurate
3D FinFETs mean lots and lots of SPICE runs even with Custom 2.0
Custom 2.0 is design data dependencies, NOT design data managment
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