( ESNUG 515 Item 4 ) -------------------------------------------- [11/29/12]
From: [ Jim Hogan of Vista Ventures LLC ]
Subject: Custom 2.0 means that SPICE runs must BOTH be fast AND accurate
Hi, John,
With Custom 1.0, SPICE simulation speed and capacity came at the expense
of precision.
For the Custom 2.0 retooling, such a tradeoff will no longer be acceptable
to analog designers. In fig 7, we look at simulation and analysis across
a scale showing the increasing effort and precision required.
Figure 7: Custom 2.0 verification technology landscape
The applications range from custom digital, memory, clock and I/O, and mixed
signal through analog to radio frequencies (RF), microwave, and micro-
electromechanical systems (MEMS). The analysis gets more complex at the
circuit level as well as the whole system level, ranging from one-physics to
multi-physics. Transient analysis is required across the broadest range,
from custom digital to microwave. From high-speed I/O's through RF, we find
various flicker, shot and thermal noise analysis. From analog through
microwave, we have harmonic analysis.
As chip designs scale to RF, microwave and MEMS, and as the need for
chip-package-board co-design increases to provide for speed and density
while reducing power and form factor, newer challenges surface. With these
trends, it is often necessary to calculate the complex electromagnetic
fields to be able to model the designs accurately.
Electromagnetic (EM) Integrity includes signal integrity, power integrity,
simultaneous switching noise analysis, and electromagnetic interference
analysis. A variety of approaches exist to calculate the electromagnetic
fields. These include 2.5D traverse electromagnetic solvers, 2.5D boundary
element/method of moment solvers, 3D quasi-static solvers and 3D full-wave
solvers.
The Custom 2.0 SPICE simulation challenge is basically, with high volume,
28-nm-and-below designs, the cost of failure is so high that SPICE coverage
becomes increasingly critical.
Here are some problem examples from traditional SPICE simulation:
- Verifying a post-layout LC-tank voltage controlled oscillator
(VCO) with 1.8 million elements, including transistors, resistors,
capacitors, and inductor took 18 days.
- Verifying post-layout SerDes I/O Macro with 12.8 million elements
could not be run.
- Verifying a post-layout 12-bit ADC with 7.4 million runtime took
36 days.
Even accounting for increasing the number of sim farms, SPICE simulation
speeds need to improve 5-10x and SPICE simulation capacity needs to improve
100x when compared with traditional SPICE simulators. Furthermore, both
improvements must occur without giving up any accuracy.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
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Custom 2.0 is design data dependencies, NOT design data managment
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