( ESNUG 514 Item 7 ) -------------------------------------------- [11/16/12]
Subject: 318 engineers surveyed on top core frequencies and NoC use issues
> According to Semico, designs in 2013 will have an average of almost 90
> different IP cores.
>
> - Jim Hogan in ESNUG 511 #1.
From [ Jack Browne of Sonics ]
Hi John,
In October, 2012, Sonics had a consultant run a blind, anonymous worldwide
survey covering on-chip communications networks.
Overall 318 engineers and managers responded. Since only 6 respondents
completed the survey after Jim Hogan's ESNUG 511 was posted, it didn't
influence the final results. Below are some of the key survey findings.
TARGET CORE SPEEDS FOR 2013 DESIGN STARTS
283 respondents, or 89 percent of the 318 total, gave the target speed for
the fastest cores planned for SoC design starts within the next 12 months.
There was a wide, somewhat even distribution of target speeds.
"What speed are you targeting to have your fastest cores run for
your organization's SoC design starts within the next 12 months?"
It is noteworthy that the majority (51%) were targeting a fastest core speed
of at least 1 GHz! Gigahertz designs are now truly in the mainstream.
PROBLEMS IMPLEMENTING ON CHIP COMMUNICATION NETWORKS
Engineers said the two biggest headaches for implementing OCCNs were meeting
PPA product specs for performance, power and area (45%) and balancing
frequency, latency and throughput (42%) -- both directly related to the
gigahertz design issues mentioned above.
"What are your organization's 2 biggest challenges
when implementing an on-chip communication network?"
Meeting product specifications (PPA) ############### 45%
Balancing frequency, latency, throughput ############## 42%
Integrating IP elements/sub-systems ############# 37%
Getting timing closure ############ 35%
Managing routing congestion ######## 25%
Do not know ### 8%
Other # 3%
Second tier challenges were integrating IP elements/sub-systems and getting
timing closure, both key problems for IP reuse and faster time-to-market.
TOP CRITERIA FOR SELECTING A NETWORK-ON-CHIP (NOC)
We asked the survey participants for their top 3 criteria for selecting a
Network on Chip (NoC).
"What are your top 3 criteria for selecting
a Network on Chip (NoC)?"
Scalable-Adaptable ######################## 49%
Quality of Service (QoS) ################### 38%
System Verification ################### 38%
Layout Friendly ################## 36%
Power Domain Partitioning ############### 31%
Memory Optimization ########### 22%
Virtual Channels ########## 19%
Security ######### 18%
Cache Coherency ######## 17%
Chip-Package-Board/
Interposer support ####### 14%
Other # 2%
We were happy to see the designers in the survey effectively said that they
wanted what our Sonics SGN NoC already has:
- Easily scales to 150+ cores; only limit is verification runtime.
- Credit-based, non-blocking flow control for killer QoS.
- Automatic UVM-based verification of the configured network.
- Virtual Channels means it's layout friendly.
- Power/clock domain crossings can be anywhere in the network.
- Does >1 gigahertz data rates.
I hope these survey results help your readers considering commercial NoCs.
- Jack Browne
Sonics Inc. Milpitas, CA
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