( ESNUG 513 Item 4 ) -------------------------------------------- [11/01/12]
From: [ Shawn McCloud of Calypto Design ]
Subject: 744 engineers surveyed on what HLS integrations they want next
Hi John,
For the fourth year in a row, the Mentor Catapult C Synthesis group (which
is now part of Calypto) ran its annual blind survey on High Level Synthesis
(HLS). 744 engineers responded.
"What *3* technologies are the most important to
integrate with High Level Synthesis?"
RTL synthesis ################## 55%
Power analysis/optimization ################# 53%
C-to-RTL formal proof ########## 30%
Design For Test ########## 30%
Place and Route ########## 29%
Mixed C/RTL functional simulation ######### 26%
Floor planning ####### 22%
TLM virtual prototyping ##### 16%
RTL linting ##### 14%
Emulation #### 12%
Other # 2%
This data above was from our worldwide customer/prospects list plus an
external rented list.
To check for potential survey bias, we ran the exact same question only
on that external rented list. 401 engineers responded.
"What *3* technologies are the most important to
integrate with High Level Synthesis?"
RTL synthesis ################# 52%
Power analysis/optimization ################## 55%
C-to-RTL formal proof ########## 31%
Design For Test (DFT) ######### 28%
Place and Route ######### 27%
Mixed C/RTL functional simulation ######### 28%
Floor planning ####### 21%
TLM virtual prototyping ###### 18%
RTL linting #### 13%
Emulation ### 10%
Other # 1%
Notice on BOTH lists that:
The 1st tier of responses (~53%), was a 2-way tie:
Power analysis/optimization,
RTL synthesis
The 2nd tier of responses (~30%) had a 4-way tie:
C to RTL formal proof,
Design for Test,
Place and Route,
Mixed C/RTL functional simulation
For us, this was good news because this year we integrated power and RTL
synthesis into our new Catapult LP tool which we announced at DAC.
Specifically, it lets engineers to report area, performance and all the
flavors of power (peak, average, leakage) from C++ or SystemC. Engineers
use this inside Catapult to make better hardware architecture decisions
for power. The new tool also uses PowerPro sequential analysis for higher
clock-gating efficiency in its generated RTL output.
With regards to integrating HLS and SLEC formal verification, stay tuned...
- Shawn McCloud
Calypto Design Systems San Jose, CA
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