( ESNUG 512 Item 6 ) -------------------------------------------- [10/18/12]
Subject: Mehmet has serious doubts about Solido's 6 sigma coverage claims
> Simulating 1 million Monte Carlo (MC) samples takes too long. Simulating
> 1 billion MC samples? Not even possible! Solido HSMC makes it possible
> to actually *analyze* millions to billions of MC samples while only having
> to simulate a few thousand -- the ones at the tails. That's the essence
> of HSMC's value.
>
> SPICE itself is not statistical, but the parameters of device models used
> by SPICE may be statistical.
>
> - from http://www.deepchip.com/items/0505-06.html
From: [ Mehmet Cirit of Lib Tech ]
Hi John,
I enjoy reading your posts.
I am wearing my engineer hat today, so I thought I'd point out some of the
fundamental flaws in Solido's 6 sigma coverage claims:
1. Solido claims that by taking samples at the tails, they can cover
as much terrain as if they did millions or billions of Monte Carlo
SPICE simulations. Intrinsic in this claim is that the regions of
design interest are the tails of the distributions.
This is only partially true.
If we are talking about a variable like threshold voltage, the bigger
the increase, the bigger would be the delays. In such a case,
sampling the tail make sense. However, circuits are very non-linear
systems. For example, still talking about the delay, if you increase
the width of a transistor, it will switch on faster. However, its
driver will slow down because of the increase in the gate capacitance
of the bigger transistors.
In this case, best case delay will happen NOT at the tails, but closer
to the center. Similarly for the worst case. Depending on the size
and driver of each transistor, each can change the width up or down to
have the worst total delay.
Unfortunately, most of the variational parameters fall into this
category. Depending on what you may call "failure" criteria, the
region of interest varies, and when there are hundreds of variables,
there is no way of guessing where the region of interest could be.
Definitely it is not at the tails.
2. If you have apriori knowledge of the region of interest, then there
is no need for Solido to do anything else. There is no need to do
simulation to find out your coverage. Just look it up from the
Handbook of Mathematical Functions. I bought a copy at graduate
school, it is still on my shelf.
3. It is a fallacy for Solido to claim that there is a random variable,
ranging from minus infinity to plus infinity, controlling the length
and width and various other parameters with some linear relationship.
If you keep pushing this model towards the tails, you can easily get
into a region where transistor length and width and other parameters
may start assuming a non-physical character, like negative values, or
push the device models into a region which may be contradictory, or
the models may not extrapolate properly, or fail mathematically.
What may happen at the tails are two fold:
(a) such devices may not exist at all, and
(b) interpolated device models may be not realistic
and may not interpolate.
The consequence of (a) is that Solido can not really calculate the
size of the sample space and can not make any coverage claims as a
result. Consequence of (b) is if the SPICE models are not reliable
in this region, then none of the Solido results are reliable.
4. These distribution models are only reliable for relatively small
variations around the center. Solido can not really extrapolate
them beyond the narrow region used in creating them in the first
place. Unfortunately, that region is not specified in the models.
Any Solido variation assumptions outside that region are suspect.
Finally let me point out that Solido's 6 sigmas could be very deceptive
especially when you talk about local random variations. For example, if
you qualify a 6 transistor RAM cell to have 1PPM failure under random
variations, and if you have 1 million of them on a chip, that chip will
always have one failure, for sure. You need much higher level 1PPT
relibaility from low level components to have 1PPM reliability at the
chip level.
- Dr. Mehmet Cirit
Library Technologies, Inc. Saratoga, CA
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