( ESNUG 511 Item 6 ) -------------------------------------------- [10/09/12]
Subject: Hogan compares Sonics SGN vs. ARM NIC 400 vs. Arteris FlexNoC
From: [ Jim Hogan of Vista Ventures LLC ]
Hi, John,
Below is my grid comparing the current commercial Network-on-Chip (NoC) IP.
In it, I compare NoC IP from Sonics, Arteris and ARM, according to metrics
I describe in my prior "commercial NoCs evaluation metrics" section.
|
Company
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Sonics
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Arteris
|
ARM
|
|
Product
|
Sonics SGN
|
FlexNoC
|
NIC 400
|
|
Performance, Power, Area
|
>1 GHz Performance, power management signaling and fully clock gated, efficient gate count.
|
533 MHz, Power Compiler based clock gating, and good area at lower frequencies.
|
533 MHz, Power Compiler based clock gating, good area.
|
|
Scalable-Adaptable
|
Scalable architecture supports a large number of number of cores (only verification limit). Fabric speed scales for narrow and fast configurations or wide configurations. Architecture supports socket based (AMBA and custom) interfaces separating cores from fabric for flexibility with chip modifications. Existing Interfaces with other fabric IP components for optimal topology configuration.
|
Flexible multiplexer/de-multiplexer based switches. Modular register slice anywhere in the network. Network interface unit
|
Bus matrix style network (not packetized). Multi-layer design. AMBA interface support.
|
|
Quality of Service (QoS)
|
Initiator-based QoS, with credit-based flow control. Non-blocking.
|
Initiator-based QoS.
|
Initiator-based QoS.
|
|
Virtual Channels
|
Yes, native virtual channels, with up to 16 channels per link.
|
No.
|
Yes, optional virtual channel component.
|
|
Layout Friendly
|
Multiple clock schemes supported to allow crossings anywhere in network. Virtual Channels to preserve the architect intent, when modifying network to match layout.
|
Span distance with pipe point; adds gates and latency.
|
Split bus matrix. Network configured by user.
|
|
Power Domain Partitioning
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Unlimited number of power and clock domains. Flexible domain crossing can be placed anywhere in the network. Fast hardware controlled domain for power sequencing.
|
Domain crossing at edge of network.
|
Component based, configured by user.
|
|
Memory optimization
|
Non-blocking fabric enabled by virtual channels combined with credit-based quality of service algorithms. Optional DRAM scheduler can be added to the network.
|
Initiator-based QoS. Optional memory scheduler IP available.
|
Initiator-based QoS with optional components like virtual channels to help with blocking.
|
|
Cache coherency
|
ACE-Lite support.
|
ACE-Lite support.
|
ACE-Lite and CCI-400 external IP for full coherency.
|
|
System Verification
|
Automatic UVM based verification of configured network (includes Synopsys VIP).
|
Proprietary verification scheme.
|
AXI Protocol compliant.
|
|
Security
|
Multi-level firewall (superset of TrustZone support).
|
Trustzone support.
|
Trustzone support.
|
|
Chip-Package-Board /Interposer Support
|
Wide I/O enabled with native fine grained multichannel memory capabilities.
|
Wide I/O enabled with optional multichannel memory.
|
No.
|
My bottom line opinion of each of the above vendor's commercial NoC offering:
- SONICS is the trusted gold standard for On-Chip Networks, this is
their core business, with over 1.5 billion chips shipped today.
Their Network-on-Chip IP meets the needs of current SoCs in terms
of performance, power and area, and the growing number of CPUs.
- ARTERIS. Their business focus is Network-on-Chips. The question
is if they can keep their product on the CPU performance curve,
and handle the growing number of CPUs on SoC's today.
- ARM is the CPU supplier for the masses. Network-on-Chips, outside
of their CPU blocks, is secondary to their main product focus.
The question is can their interconnect solution keep pace with
their CPU roadmap?
To be complete, it is also worth mentioning Synopsys' role in this space.
Synopsys provides only DesignWare AMBA parts to be assembled and verified by
the user. All additional features like QoS and security must be implemented
manually by the chip designer.
This competitive comparison is the last element of my Meta map. I hope my
analysis is useful to SoC design engineers. If I overlooked a vendor, or
some of the ones I listed have updates or things I missed, I look forward
to them filling it in this framework.
I encourage you to do your own diligence.
Your NoC must be reliable -- if it doesn't work, the chip is a rock.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
Editor's Note: As mentioned earlier, Jim's on the Sonics board. - John
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