( ESNUG 511 Item 3 ) -------------------------------------------- [10/09/12]
Subject: Exploring a designer's Make-or-Buy decision for On-Chip Networks
From: [ Jim Hogan of Vista Ventures LLC ]
Hi, John,
End user experiences drive SoC requirements -- the SoC architect must work
with an increasing number of 3rd party IP suppliers to support the all the
functionality demanded by users. Design starts by selecting:
1.) the CPU or CPUs
2.) related GPUs and DSPs
3.) memories used throughout
4.) additional special IP
Once all IP is selected, you must construct the SoC -- which is
traditionally done by internal chip design teams who developed their own
in-house proprietary on-chip interconnect bus -- or the use IP "building
block" components to construct their chip's interconnect bus.
Given the size, speed and complexity of most consumer SoCs, constructing a
proprietary On-Chip Communication Network (OCCN) can be an intensive
undertaking. As such, more companies are evaluating whether they are better
off instead utilizing commercially available on-chip network IP to make
network creation far more "turn-key". This 3rd party OCCN IP is custom-
generated based on a system's connectivity requirements like: heterogeneous
interface protocols, performance, clock and power domain requirements.
This OCCN methodology usually includes testbenches plus verification IP.
On-Chip Communications Network
Source: Sonics Inc., 2012
The chip designer's make-or-buy decision fundamentally comes down to:
1.) overall cost
2.) engineering resources, and
3.) time to market.
Further, considerations must go beyond the initial SoC design and into how
the investment will scale for derivative SoCs. The increasing cost of
SoCs drives a need to design one SoC for multiple markets where not all of
the functionality of the SoC is in use. Many SoC-based devices also have
multiple usage scenarios within a given market, such as music playback, web
searches, and making phone calls on a smartphone.
SoC architecture choices must consider how to best address design elements
such as:
- OCCN Product Choices. There are multiple types of interconnect
fabrics available from commercial vendors to allow organizations
to generate the most efficient network for a given set of
connectivity, speed and area requirements.
1. One choice typically include a packetized/serialized
routed network, commonly known as a Network-on-Chip (NoC).
The advantages of a NoC are scalability and speed.
2. For connections that require low latency, a network that
transfers address-and-data simultaneously on a crossbar
topology structure is the best choice.
3. Low speed peripherals that often have to span long distances
on the chip require a low-speed serialized network.
In practice, most SoCs will require combinations of these structures
in the same chip.
- Processor Speed. Often the only way to meet gigahertz system
frequency requirement within a tight market window is to purchase
commercial IP. The commercially available IP today supports SoCs
with fabric speeds up to about 2 Ghz. (Bus speed typically runs
at 1/2 processor speed -- so the commercially available on-chip
network IP can support CPU/GPU/DSP speeds up to 4 Ghz.) Designs
beyond this speed, typically used in networking applications, will
typically require a custom interconnect fabric.
- Number of Heterogeneous Cores. Every heterogeneous core (CPU,
GPU, DSP, etc.) has a role in the system performance. At some
level, say more than 30-40 heterogeneous cores, engineering
resource limitations make it extremely difficult to meet market
windows with a custom designed network. In contrast, a commercial
on-chip network can be readily configured to support this number
of cores. Commercial on-chip network offerings are designed to
meet the demands of many customers, and offer a broad range of
capabilities that would be too costly to develop internally.
Companies specializing in on-chip communication networks are
financially motivated to innovate. Further, they can amortize
the expensive burden of innovation across multiple customers.
- Bus speed. If you have poor bus performance it doesn't matter
how fast your processor runs. As mentioned in the processor
section, current commercial on-chip networks can run up to 2 GHz.
- Clock domains. Multiple heterogeneous processors and cores
require many clocks -- synchronous, asynchronous and mesochronous
(globally asynchronous, locally synchronous). A 28 nm SoC can
have as many as 20 clock domains.
- Power domains. With the importance of battery life for mobile
devices, managing the power of a SoC, including the ability to
power off unused blocks, will give the best battery life. Today's
28 nm SoCs are using as many as 10 power domains to meet these
performance and battery life requirements.
- Layout Friendly. While the system architects do their best to
balance system performance based on a preliminary floor plan,
when the actual chip is laid out it is likely that there will be
changes. Therefore it is important the on-chip network minimize
or eliminate any effects on the system performance based on
physical layout changes. Adding HW pipeline stages to maintain
performance and to ease timing closure should not affect the
system QoS. It's important that the on-chip network support a
logical topology that is independent of the physical topology.
- Identifying critical network traffic data flows. The SoC designer
must identify what the crucial interactions between his key IP blocks
are that must take first priority. Quality-of-Service (QoS) must
honor the architect's intent so that this critical network traffic
gets top priority, even as the number of cores scale up.
- Memory subsystem. Multiple memory transactions are funneled into
a shared memory subsystem -- this competition among cores for
memory bandwidth may degrade system performance by wasting cycles.
Minimizing wasted cycles is fundamental to the end user experience.
For example, the latency to the main memory may impact the speed
of internet browsing.
- IP selection/integration. The on-chip network must make selecting
3rd party IP easy by:
1. supporting many interface protocols (e.g. AMBA, AXI, OCP)
2. supporting many data widths,
3. supporting many frequency domains, and
4. supporting many power domains.
Independent IP blocks are becoming dominant in SoC designs; they
are expected to account for as much as 80% of the SoC die area in
just a few years. This means that your internal IP must conform
to and be compatible with that outside IP. Commercial on-chip
network suppliers often see lots of heterogeneous IP from many
customers and designs. This gives them expertise and insight into
the 3rd party IP corner cases that your engineers will not have.
- Features. Additionally, many commercial networks include features
like QoS, security, and error detection. When designing a custom
on-chip network all of these features must be explicitly designed,
requiring additional resources and time. In addition, many
commercial on-chip networks include design tools that allow for
network optimization to balance of performance and chip area.
The ultimate goal of a SoC's on-chip communications network is to achieve
better overall SoC performance and lower power at a lower cost. Regardless
of whether you build your own on-chip communications network, or buy the
commercially available on-chip network IP, you will need to:
1. have the dataflow efficiency to get the most performance
from your system,
2. maximize your DRAM utilization,
3. partition your design to lower power consumption, and
4. insure partitioning gets easy physical layout timing closure.
Finally, your on-chip communications network must be sufficiently flexible
and scalable to satisfy many changing markets.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
Editor's Note: As mentioned earlier, Jim's on the Sonics board. - John
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Related Articles
Hogan outlines key market drivers for Network-on-Chip (NoC) IP
Common definitions of On-Chip Communication Network (OCCN) terms
Metrics checklist for selecting commercial Network-on-Chip (NoC)
A detailed discussion of On-Chip Networks with Virtual Channels
Hogan compares Sonics SGN vs. Arteris Flex NOC vs. ARM NIC 400
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