( ESNUG 511 Item 1 ) -------------------------------------------- [10/09/12]
Subject: Hogan explains the fundamental market drivers for On-Chip Networks
> A great majority of people believe that a network-on-chip (NoC) is just a
> bus matrix interconnect. This is not so.
>
> - from http://www.deepchip.com/items/dac12-02.html
From: [ Jim Hogan of Vista Ventures LLC ]
Hi, John,
I noticed in the article on IP reuse tools as the #2 user pick for DAC, the
respondent who discussed Sonics SGN Network-on-Chip (NoC) IP pointed out a
common source of confusion. There is a category of On-Chip Communications
Network technology that is extremely important for multi-core SoCs, yet
still ill-defined, and I think as a result, not well understood.
As a long term investor of Sonics -- and recently a board member -- I have
constructed a Meta map of this area for my own understanding. I would like
to share it with your readers for their use. It covers everything from
market drivers, terminology, make-or-buy, and metrics and rankings for
commercial Network-on-Chip IP vendors. As always, I welcome input to help
add clarity and understanding.
Mobile consumer devices are driving SoC growth, led by smart phones, solid
state memory devices and tablets. Users want their applications to run
fast, and they want to have the device run for a day without recharging.
Apple's iPad has raised consumer's expectations with regard to how well HW
and SW work together.
Steve Jobs taught us it's all about the user experience. That translates
into hardware requirements such as performance and battery life. It also
translates into display quality. All this for example has been manifested
in the Apple roadmap with the iPhone 5.
Source: Gartner, Dec 2011
As Moore's Law keeps pushing forward with shrinking process nodes and an
increasing number of transistors, SoC designers are using all the additional
real-estate for massive function integration, including control, security,
graphics, video and audio. For example, among other design elements, the
iPhone 5 gives us high density video on a better display, with higher
bandwidth (4G LTE) and extended battery life.
---- ---- ---- ---- ---- ---- ----
As a result of this massive function integration, the SoC world is now
multi-core. Further, the number of cores on each SoC is increasing
dramatically as designers add more and more functionality in pursuit of
the ever-increasing user experience. According to Semico, designs in 2013
will have an average of almost 90 different IP cores.
Increasing number of IP cores in SoCs
Source: Semico Research, May 2012
As an example of a multicore design, shown below is Qualcomm's Snapdragon.
Snapdragon is currently driving the vast majority of the Droid smartphones
on the planet. The multi-core design challenges are compounded by the use
of heterogeneous architectures for higher scalability and flexibility,
along with distributed DMA to remove centralized memory bottlenecks.
Additionally, there is increasing software complexity to enable reuse of
multi-platform SoCs -- the software programmability broadens the SoC's
market coverage. More and more of the actual system value is being realized
in the SoC, as witnessed by Apple's A6 processor in the iPhone 5.
Snapdragon S4 Processors (courtesy of Qualcomm)
Until one to two years ago, SoC frequencies were commonly less than 500 Mhz.
In contrast, smart phones, tablets, and netbooks shipping today typically
have frequencies that are between 800 MHz to 1.4 GHz. They contain both
single and dual core processors, and typically have 60 to 100 IP cores.
---- ---- ---- ---- ---- ---- ----
Looking at 2013 and beyond, we are moving from Mhz SoCs to true Ghz SoCs.
These devices will have next-generation dual- and quad- core processors at
1 to 2 Ghz, with an additional processor for low-power, and a total of 80 to
150 IP cores on each SoC.
Semiconductor companies must keep pace with these demands, including meeting
G Hz device performance. Today's new designs are being developed from 32 nm
down to 20 nm.
20 nm is 200 angstroms, or only 200 hydrogen atoms or 80 copper atoms wide.
This means the problems are atomic-scale, where process variability is a
major problem. Moore's Law is flattening out for performance and power;
we can no longer expect the same scaling we've had for so long.
---- ---- ---- ---- ---- ---- ----
As a result, often designers cannot meet a desired frequency, and their
fix is to turn down the clock rate to get a product to market. However,
although software applications may not care about absolute clock frequency,
people do -- the system companies that fail at delivering performance will
be casualties in the evolution of mobile devices.
There is no point in putting a high-count multicore processor on a chip if
you can't be certain that it's safe to turn on all the cores at once. It
would be like turning on your microwave, toaster, blender and space heater
all at once on the same circuit, and expecting it to work.
---- ---- ---- ---- ---- ---- ----
The logical topology must be optimized for application quality of service
(QoS), so that the more important traffic can pass first. At the same time,
the physical topology must be optimized for frequency (performance) and
layout (area), such that you can be assured of performance in spite of place
and route. The on-chip communication network can have a major role in this
optimizing the logical topologies so that the physical synthesis will be
convergent.
---- ---- ---- ---- ---- ---- ----
Memory is the most contested resource. Multiple processors may operate on
same data and the on-chip network must ensure the data arrives when the
processor needs it to run the software application. You can't afford to
close timing and then find out it doesn't work because you didn't take the
system requirements into account when your routed the memory traffic.
---- ---- ---- ---- ---- ---- ----
Power consumption is an enormous issue - the best way to save power is not
to turn it on. We see more and more use of "dark silicon" - as coined by
Mike Muller, CTO of ARM - to reduce system power consumption. The goal is
to keep most of the silicon dark, most of the time. If it's not going, it's
not glowing.
Today's SoC design is more a function of the application, rather than the
application being a function of the SoC. Predicting application usage can
drive power partitioning. You save power by partitioning your design into
domains, then scheduling when these domains are turned on and off; the more
domains you have, the closer you get to an asynchronous design. In turn,
the use of power domains can create unique verification challenges, which
must be addressed by up front strategies.
Dark Silicon (courtesy of Aggios)
Example: smartphone app
processor: green cores powered for audio playback usage, all other
cores and subsystems are "dark silicon" (powered off)
The SoC world is an assembly of cores, other IP blocks, I/O's and memory.
Making all this IP work as intended requires System IP. This System IP
helps to integrate the rest of the IP into the SoC and test it to verify
its behavior before moving to physical implementation. System IP includes
performance analysis tools, debug tools, power management, security and
memory subsystems, and finally, the on-chip communication networks.
The rest of this paper will be focused on on-chip communication networks;
the interconnect fabric for the SoC.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
---- ---- ---- ---- ---- ---- ----
Related Articles
Common definitions of On-Chip Communication Network (OCCN) terms
Exploring a designer's Make-or-Buy decision for On-Chip Networks
Metrics checklist for selecting commercial Network-on-Chip (NoC)
A detailed discussion of On-Chip Networks with Virtual Channels
Hogan compares Sonics SGN vs. Arteris Flex NOC vs. ARM NIC 400
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