( ESNUG 504 Item 6 ) -------------------------------------------- [05/23/12]
Subject: Questions for Aart de Geus, CEO of SNPS & Lip-Bu Tan, CEO of CDNS
Cooley's DAC Troublemaker's Panel - that SNPS & CDNS chickened out on!
Date/Time: Monday, June 4, 3:00-4:00 pm
Location: DAC conference room # 256
IF YOU WANT TO ATTEND THIS DAC PANEL, SIGN-UP HERE
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For Aart -- Did Synopsys buy Magma just to take out a competitor and
justify their ever-increasing prices? If not, what can he say about
maintaining the Magma toolset?
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Aart, was there a product that Magma had that inspired you to
buy them for it?
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For Lip-Bu Tan:
Magma has several products that would enhance your protolio, how
could you pass up the chance to own them?
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To Joe and Lip-Bu:
Concerning SNPS/LAVA, how do you plan to recover from such
a strategic mistake? Aart now owns 70 percent of PNR!
MENT & CDNS are so screwed!
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To Aart:
What did Rajeev do so many years ago that caused you to hate him so?
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How much did Rajeev and Roy get to walk?
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To Aart:
Did the $188 million acquisition of Synplicity pay off? Did Synopsys
gain $188 million in revenue as a result of this merger?
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What tools will be available so I can design heterogeneous H/W (FPGA)
and S/W systems at a level of abstraction where I do NOT need to deal
with timing issues?
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Edgy question for the ghost Aart DeGeus of Synopsys:
Please confirm or deny that the EDA business is stagnant and
that IP is Synopsys' growth strategy.
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Edgy question for the imaginary Lip Bu Tan of Cadence:
How important do you see the IP business to Cadence, and aside from
acquiring Denali, what are you to doing about your trailing position
in IP?
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Aart:
Why are licenses of Synopsys tools cheaper in India, putting
US engineering at a competitive disadvantage?
Lip-Bu:
Why are licenses of Cadence tools cheaper in India, putting
US engineering at a competitive disadvantage?
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To Aart and Lip-Bu -- How much do you get in sales from having
closed, proprietary interfaces?
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My burning question to SNPS and CDNS is: why do EDA vendors
continue to claim it costs $100 m to design a chip when it is
in fact NOT true and it has effectively dried up investment
in semiconductor startups?
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For Joe, Aart, and Lip-Bu
Can Synopsys and Cadence give developers FPGA-only versions
of tools so that all their Verilog HDL IP for FPGA will not
be as expensive as Verilog IP for Asic??? (Most developers
are not develop super ASICs for super Giga speed. Most
developers in the world are doing the lower speed FPGAs.)
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To Lip Bu Tan of Cadence:
Being relatively new in verification with Cadence tools and having much
experience with other vendors, one aspect with Cadence is remarkably and
leads me to a question:
My experience is that if I have a minor bug (yes, a real bug) in Cadence
tools where a workaround is possible, this bug won't be fixed by R&D.
Perhaps they have too much work with bigger issues and improvements.
Nevertheless this bug has a potential to cost effort/time for customers.
Is this impression correct? Or is there no tight link between CDNS FAEs
and CDNS R&D so that customer feedback won't reach R&D?
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To SNPS:
What do you want to do in mixed-signal system level design?
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To CDNS:
Do we need special licences condition for SME?
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IF YOU HAVE AN EDGY QUESTION THAT I SHOULD ADD HERE, PLEASE EMAIL ME
DIRECTLY AT  WITH IT. YES, YOU'LL BE ANON! - JOHN
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