( ESNUG 503 Item 3 ) -------------------------------------------- [05/04/12]
From: John Weiland <john.weiland=user domain=abraxascorp got calm>
Subject: Blue Pearl, MENT inFact, Certe, Breker, SpringSoft Certitude
Hi, John,
Here's my report on Linters and Assertion/Testbench Coverage Tools.
Atrenta sells Spyglass, which has some fancy algorithms under the hood
(synthesis and formal checking included) so they don't like the term
"linter". It does structural, coding and consistency checks. They have
a number of other tools named "Spyglass something-or-other" for various
functions, like generating and checking constraints, doing RTL power
analysis, checking clock domain crossings, and analyzing Design-For-Test
at the RTL level. They also sell a tool called 1-Team System for analysis
of System C code, and claim they do much more than simple lint checks, but
they seem to be deemphasizing that tool this year.
Synopsys Leda linter apparently also does synthesis under the hood and is
pretty easy to use. It includes Synopsys specific rules like DesignWare
and Formality rules.
Blue Pearl Software sells a tool called Indigo that does normal linting
checks like those for DFT and reuse, and also checks for clock domain
crossing errors. A couple of years ago they told me it does not do
synthesis like Spyglass so it runs faster. They said that for clock
issues it is best to check the whole design at once, and they have run
it on a 42 M gate design so it has the capacity needed to do that. New
for this year is html reporting.
Aldec sells a linter that they claim is similar to Atrenta Spyglass
(I didn't see it). It supports Verilog or VHDL, using the STARC, RMM
and DO254 rule sets.
ASIC Analytic is creating a tool that sounds similar to Atrenta but I
don't know if it's as sophisticated under the hood. It checks basic
linting, clock domain crossings, voltage islands, scan chains, etc.
They emphasize ease of use; it has no setup files or command line options.
The tool is expected to be out in late summer and anyone who saw the booth
at DAC (and I suspect anyone to contacts their sales rep) can get a free
demo license.
Real Intent has a formal checker called Ascent that does linting as well.
Assertion/Testbench Coverage Tools:
Mentor bought Lighthouse and got a tool they call inFact which is similar
to the tool from Breker. The user creates rules describing a protocol in
a format similar to BNF, with actions described in Verilog, System Verilog,
C/C++, System C, etc. inFact outputs testbenches that attempt to maximize
functional coverage.
Mentor has a tool called Certe Testbench Studio that allows a verification
engineer to create and analyze a System Verilog testbench graphically. It
mainly supports the OVM standard but they have had customers using it for
VMM. They say it is very useful for visualization of class structures, etc.
for engineers who are relatively new to System Verilog.
Mentor had a tool that measured assertion density (i.e. do you have enough
assertions in your code?) but it has been folded into Questa. I know some
experienced designers who have had courses that cover assertions with
examples like "these two signals are always complimentary". They conclude
that assertions are some stupid fad that they hope will blow over soon.
A tool that tells folks like this that they must add more assertions will
not be popular.
Breker Verification Systems sells a tool that generates testbenches similar
to Mentor's inFact tool, although they say is works very differently and
they claim inFact is aimed primarily at Questa. The input is BNF, C or C++
and the output is a testbench in Verilog, C, C++, Vera or System Verilog.
Breker says they keep their graphs smaller than the Mentor tool because
they can use C/C++ and claim better performance as a result of that and
the user defined constraints. They do coverage graphically, which they
say is easier for the user to understand. They use model based generation
to help know when they are done -- the age old question in verification.
SpringSoft sells Certitude (which they got when they bought Certess). It
tries to measure the quality of your testbenches by inserting bugs into
your code and seeing if the testbenches find them. This is a nice addition
to code coverage and functional coverage.
Axiom sells a tool called Protometer, which takes an executable test plan
in XML and can measure protocol coverage, allow graphical debug and generate
vectors. They also have some sort of test planner called Maverick, but I
didn't get any information.
Zocalo Tech sells a tool that manages System Verilog assertions. It helps
identify critical signals, allows graphical coding of constructs, and helps
debug assertions.
- John Weiland
Abraxas Corp. Columbia, MD
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