( ESNUG 500 Item 7 ) -------------------------------------------- [03/08/12]
From: Phil Tharp <ptharp=user domain=highipdesign not mom>
Subject: I designed a USB 3.0 core using SystemC and Forte Cynthesizer
Hi, John,
I started HighIP in order to create high-level IP in SystemC that could be
synthesized to Verilog RTL using Forte's high-level synthesis. (Previously,
I had developed a USB 2 device and host controller for FPGAs as "Vreelin
Engineering".) If you buy a USB 2 device controller from Xilinx, you are
buying my core. I wanted to implement a USB 3 core, but I really didn't
want to use Verilog again, and I thought SystemC was an attractive
alternative.
My first question was, is it practical to write a USB design in SystemC,
and to use high-level synthesis? My second question was would I like
doing it? (Life's too short to use lousy tools.)
Before jumping in to do the USB 3 core, on my USB 2.0 controller I used
Forte Cynthesizer to synth to Verilog, then Xilinix XST for logic synthesis
and finally Xilinx's MAP and PAR for place and route. My target
implementation was a Xilinx Spartan-6 with an SMSC PHY on a daughter card.
A USB controller is all control -- there are no data path components in it.
The protocol on the USB side is very strict -- data and control signals
appear and have to be responded to at exactly the right times or the
protocol breaks. Used a ULPI interface from the PHY to the controller.
On the processor side of the controller, I used an ARM AXI bus interface.
Xilinx has recently released an EDK that lets you create a microBlaze,
cache, and memory attached to an AXI bus that you can attach your
peripheral to.
I implemented both a slave and a master so the device controller could do
DMA transactions to the processor's memory.
The AXI bus has a well-defined protocol, but there is a fair amount of
leeway allowed between when a transaction is requested and when it starts.
This makes coding using HLS pretty natural. It's easy to tell Cynthesizer
to pipeline a loop to have data go out on or come in from the bus every
cycle, and if you can let Cynthesizer decide when to this way compared to
having to write the state machines by hand in Verilog.
When I was writing the DMA routines in the AXI master interface, I could
take a lot of the C code that I had previously written for the firmware that
supported my old Verilog core and just use that (the old core used an LMB
interface that doesn't support DMA). It was written in C, and putting it
into a SystemC routine that would become hardware was trivial.
I call this mushware, since it can go in software or hardware by simply
moving the boundary of the synthesis.
The statistics:
- 4164 lines of SystemC code:
- 1593 lines deal with the AXI bus interface, master and slave
- 1552 lines deal with the USB interface
- 1019 lines deal with everything else (clock domain crossing,
buffer management, constant definitions,
and hierarchy)
- 16678 lines of generated Verilog
- 3527 slice LUTs on the FPGA (a Xilinx Spartan 6)
- USB bus runs at 60 MHz (required)
- AXI bus runs at 100 MHz
- FPGA implemented a mass storage device, attached to a PC or a Mac
- The protocol was verified using a protocol analyzer
- Throughput maxed out at 52MB/sec, which is the practical
maximum of a USB "high-speed" device connected to a PC
The pros:
The biggest Forte pro was the ease of doing the design. Next biggest pro
was flexibility. I completely re-architected the queueing mechanism and
had it working in just 3 days. It would have taken me 2 weeks rewriting
Verilog RTL and getting it working!
Also, it was easy to take the pieces and rearrange them to implement an
embedded host controller on the AXI bus. And, all of the code for this
project gets reused in the USB 3 implementation that was the original
motivation for the project.
Comparing this implementation to my "Vreelin" device core is not exact,
since this SystemC version has a much more sophisticated buffering scheme
than the first Verilog one does. Nevertheless, if I compare just the "SIE"
(the part on the USB bus clock side of the design -- the Serial Interface
Engine), the new one is about 33% bigger than the old one (2154 LUTs to
1610 LUTS). I estimate that the buffering accounts for about 1/3rd of the
design, and that is split evenly over the AXI bus interface and the SIE.
That would account for the increase in size of the SIE, so my conclusion
is that the generated code is very close in size to my old hand-generated
code. My "Vreelin" device core is the smallest available to my knowledge.
The cons:
There is still room for improvement in this design flow. SystemC leaves a
lot to be desired when it comes to error messages. Since all I was using
is gcc, simple mistakes can be hard to track down. We really need a good
SystemC IDE.
Cynthesizer is pretty mature -- I didn't run into bugs very often -- but to
get it to work with protocols, you have to use pragmas. There are only a
couple of pragmas that you have to use, but understanding where they go and
what they do is not particularly simple. If you don't understand hardware,
you're going to have a hard time.
The Forte people say that Cynthesizer isn't going to replace HW designers,
and they are right. On the other hand, having designed hardware at RTL and
now at SystemC level, I'm not going back. I don't get my thrills from
writing the same state machine by hand in Verilog for the umpteenth time.
- Phil Tharp
HighIP Design Company Mountain View, CA
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