( ESNUG 500 Item 5 ) -------------------------------------------- [03/08/12]
Subject: We cut another 9% of power using the Calypto RTL PowerPro tool
> Regardless, if there's only one take away that I want your readers to have
> here is that Calypto does RTL power optimization, too! PowerPro looks
> across 100's of cycles, while Atrenta Spyglass Power & Apache PowerArtist
> are limited to only a few clock-cycles.
>
> - Shawn McCloud
> Calypto Design Systems Santa Clara, CA
From: [ Lunar Wolf Power Ranger ]
Hi, John,
Please keep me anon. Company policy.
I used Calypto PowerPro for power analysis and optimization of a 3 M gate
design, along with Calypto SLEC to formally verify the power-optimized
RTL against our original Verilog RTL. Below are my results.
Our test case was an existing 3 M gate design that we had already hand
tuned for power. We spent 2 to 3 man-years over the life of our design
just clock gating it!
It took us only about 5 hours to get another 9.4% power reduction from
Calypto, including:
1) Using PowerPro perform the RTL level optimizations, and
2) Using SLEC to formally verify the optimized RTL.
It took me around 2 days to set up the Calypto tools, with remote support
of a Calypto AE. For a second design, I expect set up to only take 1 day.
Before Calypto After Calypto Change
--------------- -------------- ---------
Power 32 (mA) 29 (mA) - 9.4%
Area 6.4 M sq mm 6.45 M sq mm + 0.8%
Gated flops 65% 75% + 15%
Timing clean passed timing N/A
Based on the results we saw, you can use Calypto PowerPro not only to get
additional power reduction on existing designs, but also to save you
man-years of doing manual power optimization in the first place.
Time
---------------
Calypto set up 2 days
(1 day expected for 2nd design)
Calypto PowerPro 2.5 hours
(for all optimizations)
Calypto SLEC 2 hours
Total 2 days plus ~5 hours
(includes both set up and runtime)
Manual power optimization 2-3 Man years
(over the life of the design)
The run above and the results were our second run, after we disabled some
PowerPro optimizations that were too difficult to prove in SLEC. (We only
used clock-gating optimization, not memory-gating power optimization.)
PowerPro came up with clock gating that our designers wouldn't have come up
with. I would break up clock gating into 3 general types:
1. Synopsys Power Compiler: Gating for individual blocks, low grain
optimization on individual registers. E.g. for a 100,000 flop
design, Power Compiler looks at 20,000 targets of 5 flops each.
2. Designer inserted: Coarse grain optimizations at the top level,
e.g. on/off switches on design unit level. E.g. for a 100,000 flop
design, the designer might look at 25-50 different blocks of 2000
to 4000 flops each, and add clock gates to each of them. These
typically turn on and off functional units depending on if they
are used or not.
3. Calypto PowerPro: Found clock gating niches between the two
granularities of #1 and #2, such as switching on and off groups
within blocks of logic. E.g. for the same 100,000 flop design,
PowerPro can also look at 1000 different targets of 100 blocks
each. The logic to control this is more complicated than
designers can do manually, since they must work through so many
conditions, but the potential power savings is higher as parts of
functional units are disabled on a very dynamic basis.
We took the PowerPro Verilog RTL output and immediately ran it through their
SLEC for equivalency checking/formal proof vs. the original RTL; the two
tools are integrated, so this step was straightforward. Since SLEC was new
to us, we also ran some NC-Sim simulations to see if it was accurate, which
it was. Because of SLEC, we didn't need to do extensive verification by
running the entire suite in NC-sim. We wanted to run the simulations anyway
to establish the new power consumption results.
POWER ANALYSIS/ESTIMATION ONLY (NO OPTIMIZATION), TIME FOR EACH CYCLE
We found that using PowerPro for power analysis alone at the RTL level was
very useful (i.e. even without optimization). PowerPro has embedded logic
synthesis, so its power estimation correlated closely enough with our final
gate-level power results to be meaningful. I want to emphasize that
PowerPro's results are *estimations only*, and not for "sign-off", since the
design has not yet actually been implemented at the gate-level.
But the important part is that PowerPro is accurate enough to let you know
if you are making the correct design decisions and trade-offs when you do
your optimizations. (For our test case Calypto predicted 26 mA, or a ~12%
saving in dynamic power versus an actual 29 mA, a savings of around 9.4%;
which correlated to within 10% of our gate-level power analysis.) The key
thing here is the power analysis time savings is huge, meaning the tool is
quite useful when you want to explore other power improvements made due to
manual Verilog RTL changes as well.
Tool Runtime Speed-up Calypto Power Savings
-------------------- --------- -------- ---------------------
Verilog RTL Level:
Calypto + SLEC 4.5 hours 5X 12%
(Calypto estimated power
savings)
Gate level sign-off:
Design Compiler+ 24 hours 1X 9.4%
Cadence NC-sim+ (Actual Calypto savings,
Power Compiler per Sign-off)
You could use PowerPro as an RTL design step and do your verification/
simulation afterward, or you could use it after RTL design and verification,
as a pre-synthesis step. It is simple to use because of its automation,
and you don't have to be a power expert.
THE GOTCHAS:
I would like to see Calypto make these improvements to PowerPro:
- Mixed language support. You can do Verilog or VHDL but not both at
the same time. Our design was almost all in Verilog, with one very
small block in VHDL; because the VHDL block was so small, we didn't
bother to do a separate Calypto power optimization run on it. It
would have been a PowerPro headache. Not worth it.
- The price of a PowerPro license is high. If they charged less,
more designers would use it.
What impressed me most is how much time Calypto can save you, both by
estimating power during RTL design, and by giving you close automated
power optimizations than you can do manually in a fraction of the time.
The potential time savings is literally multiple man-years over the life
of a design and its derivatives.
- [ Lunar Wolf Power Ranger ]
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