( ESNUG 500 Item 4 ) -------------------------------------------- [03/08/12]
Subject: Three chip designers hands-on evals of Atrenta Spyglass Power
> We would like to have some user perspective on RTL-level power analysis
> and optimization. Specifically Apache PowerArtist/PowerArtistXP and
> Atrenta Spyglass Power. We are seriously considering using one in our
> next design.
>
> - [ Puss in Boots ]
> http://www.deepchip.com/items/0495-07.html
From: [ Gozer the Gozerian ]
Hello John,
Last year management required us to reduce power by 50% and at the same time
design requirements increased by 2X. (Fun, no?) We had to come up with a
better power flow. We evaled both SpyGlass Power and Apache.
Our test design was TSMC 65 nm, 1 M gates, 97 K flops, 28 memories
After detailed evaluation, we have chosen SpyGlass Power for our next gen
chips. The key reasons for our decision:
1. Fairly accurate power estimation. SpyGlass RTL Power correlated
within 10% when comparing with final silicon power numbers.
2. The tool allowed me to experiment with the bus-width for Power
Compiler-based clock-gating, we finally picked 8.
3. We experimented with the feedback that SpyGlass Power provides
designers with missing "enable" in their "always" blocks and it
did help us with power-holes as we had some XOR trees that were
constantly being clocked.
4. Their tool accepts FSDB file instead of VCD. A plus!
5. Additionally we use Spyglass Lint and Spyglass CDC as part of our
design and this helped in reducing the tool bring-up time. We were
up and running in couple of days.
Some key SpyGlass Power features that impressed us:
- Activity reports
- Determine vector profile, active/inactive blocks
- Enable reports
- Power savings of explicit or existing clock enables
- Proposed additional clock enables and their savings
- Un-clock gated FFs with power consumption
- Power estimation of TXP design
- Matched expected estimations
- Detailed reports of leakage/internal/switching along with
different categories such as combo/sequential/clock/memory/etc.
These details are helpful to understand our chip's actual power behavior and
to pin-point what can be done for reducing it.
Here are some improvements we'd like to suggest for SpyGlass Power based on
our experience in a recent project:
1. The tool doesn't support TCL. (Supposedly Atrenta will have it TCL
ready for the next revision.)
2. SpyGlass Power has a very convoluted way of describing SGDC.
3. Its GUI needs to be improved.
4. SGDC_LIBS creation is a separate step needed before starting
power analysis. It should no be that way.
I must remain Anonymous for this post. Always appreciate your work, John!
Thanks.
- [ Gozer the Gozerian ]
---- ---- ---- ---- ---- ---- ----
From: [ Domo Arigato, Mr. Roboto ]
Hi, John,
Pl keep my name and company name/email address anonymous.
We were one of early adopters of SpyGlass Power and I'm glad to share my
experience and usage at our company. Every block owner in our company has
to perform power analysis with SpyGlass Power before signing off his block.
We chose this tool simply because clock-gating early in the design cycle
is easier/cheaper than later in the game.
SpyglassPE needs the following for power estimation
- RTL netlist (or GL netlist with SPEF)
- .lib files used for design synthesis (this is converted to SGLIBs)
- VCD/FSDB file for the intended test or functionality
SpyglassPE can
- Estimate the active power for synthesized blocks and identify spots
for dynamic clock-gating and power optimization.
- Estimate active power savings due to backend inferred clock-gating
based on clock-gating threshold.
- Estimate leakage per block or full-chip based on VT usage and
voltage/power partitioning.
- Estimate the memory active power and leakage for your stand-alone
or embedded memory macros and wrappers.
- Evaluate the total power for any given function (audio playback,
DMA transfers, AXI traffic etc) at island or SoC level.
- Analyze the dynamic power profile (transient power vs time) for any
given IP for the intended function (eg: Core running Dhrystone)
- Debug RTL and memory power for any given module in silicon and
identify/optimize components with higher-than-expected power.
Atrenta says that silicon-simulation correlation studies have shown that
SpyglassPE is within ~10% of silicon power.
WARNING: The accuracy of power estimation is dependent on
- Inclusion of all relevant RTL files in the design from top
to lowest level of hierarchy.
- Inclusion of all .libs used for synthesis (both RTL and memory).
- Full signal coverage (including all nets across design hierarchy)
in the VCD or FSDB file.
The tool provides plenty of indicators to indicate if the power simulation
report is accurate enough
Key steps for using SpyGlass Power:
1. Spyglass tool setup
2. Compiling libraries (SGLIBs) for your design. Make SURE your
std cell and mem .libs contain leakage and internal power models!
3. Add your Spyglass power analysis/reduction options.
4. Create SGDC design constraints file (pe.sgdc) for various inputs
for accurate power estimation and better reduction.
5. Run analysis and look at various reports
a. Hierarchical power reports for all three components like
leakage/internal/switching.
b. Power browser to browse the power for different modules
and cross-probe RTL/schematic to understand power hot spots.
c. Design stats to see what kind of cells are used by synthesis.
d. Power reduction report for further reducing the power in
the design, especially on clock gating
SpyglassPE limitations:
- SpyglassPE needs separate runs for reporting a hierarchical final
power summary for RTL design with and without clock-gating.
- SpyglassPE relies on VCD or FSDB to properly annotate 2D gate arrays
properly in simulation; otherwise power numbers will not be accurate.
- IT IS NOT MAGIC. IF YOU DON'T GET SpyGlassPE ALL THE CORRECT .libs
AND RTL FILES AND FULL SIGNAL COVERAGE, IT WILL BADLY BURN YOU.
GARBAGE IN == GARBAGE OUT.
I can not stress the importance enough of giving SpyGlassPE all the right
files if you want it to work correctly!!!
- [ Domo Arigato, Mr. Roboto ]
---- ---- ---- ---- ---- ---- ----
From: [ Marathon Man ]
Hi, John,
Below is my "report card" on the Spyglass Power tool.
Please keep me "anonymous" and not mention my company's name, thanks.
SpyGlass Power is just one of the many different tools like LINT, CDC, DFT,
etc., that Atrenta has integrated. The key usage model is to start power
analysis early (RTL-level) in the design development flow to determine the
effects of different ways to implement a design or ECOs. The tool has to
be very quick and have acceptable accuracy along with a good GUI.
For SpyGlass Power these are the grades I gave the tool.
Relative accuracy: B+ (needs more calibration for better accuracy)
Run times: A
Power clock-gates: A
Clock tree model: B
Support: A
Deployment feasibility: A+
Focus on needed improvements:
Ease of use was good, but did require to know the right knobs to turn in a
couple of different areas. The key for me was the tool has a very large
set of facts about power consumption and opportunities for power savings
for the design in its DB. The tool needs more simple visual methods to
show the data vs. a wall of numbers in a table format. One way is to use
colors or size of a box to show this sub element consumes X power. That
way at one glance the designer knows the which blocks consume the most
amount of power. This can also get used to show how the power would look
like if you did some optimization to the design (advice is given by the
tool), for example before and after power savings can get shown using
different size blocks vs a wall of numbers.
One of the biggest benefits of the tool it is just one of the many domains
Spyglass addresses (power, DFT, CDC, lint, constaints, physical.) The
designer is a lot more productive working in a common tool for 6 domains
vs. 6 different tools, one for each domain. We have little time to ramp up
on tools nor do we have 6 different teams dedicated to a given domain.
- [ Marathon Man ]
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