( ESNUG 500 Item 2 ) -------------------------------------------- [03/08/12]
Subject: Brett's quickie trip reports on both DVcon'12 and NASCUG'12 confs
Hi, John,
Here's my company notes on the DVcon'12 and NASCUG'12 conferences.
DVCon'12
There were 35 vendors with booths. Evidently more booths were available
originally but it doesn't look like DVcon'12 was able to fill all of the
space. Cadence, Mentor, and Synopsys each had 10x20' booths and the rest
of us slummed it with 10x10's. So, it was pretty small.
DVcon attendance
2008: ################################ 802 total (254 paid)
2009: ########################### 665 total (135 paid)
2010: ######################### 637 total (131 paid)
2011: ############################### 760 total (231 paid)
2012: ################################# 834 total (226 paid)
This is the second year that we (Forte) participated in the show after being
out of it for a while. Most of Forte' growth in 2011 came from the US and
we've started investing heavily in this area (hint: we are hiring).
I have to say, I think DVCon'12 was worth the investment this year. We had
52 "contacts" stop by the booth that were interested in SystemC and most
seemed serious. I'd say that the focus was a bit more on verification
than design but that is how it starts. There is still some skepticism in
the market that HLS tools can beat hand-coded RTL. Maybe people are
still hurting from the SNPS Behavioral Compiler experience? Don't know.
There were groups from two large customers in particular that stopped by
our booth because of interest generated by the paper that Steve Frank,
the CEO of Paneve, gave titled "Designing, Verifying, and Building an
Advanced L2 Cache Subsystem Using SystemC." There were about 40 people
in the room for that paper presentation. One key comment Steve made was
that Paneve was able to specify their design using 25 K lines of SystemC
code and synthesize it using Cynthesizer instead of 1 M lines of hand
written Verilog RTL. (Yes!)
---- ---- ---- ---- ---- ---- ----
There were 12 technical sessions at DVcon where 3-4 papers were given in
each session covering topics ranging from SystemC to low power to UVM to
formal. There were also 8 sponsored tutorials. Smartly, the DVcon exhibit
hours were short and didn't overlap with sessions giving the attendees
a chance to browse.
Some specific vendor notes:
- Verific showed a new Perl API to their System Verilog and
VHDL parsers. Their customers use these parsers to build
various products. They claimed that 12 of the 35 vendors
on the floor are Verific customers.
- Vennsa showed a tool called OnPoint. They claimed that their
tool automatically finds the root cause of functional errors
during verification, fixes them, and tells you the offending
lines of source code. (They made a very interesting comment
that 6 hours of DVCon yielded more "quality" users than 3 days
of DAC.) This was Vennsa's second year at DVCon and they
claimed attendees and exhibitors were up and they were
"super-duper happy."
- EVE showed the ZeBu-Blade2 hardware-assisted verification
platform. This is the first of their products to use the
Xilinx Virtex6-LX760 FPGAs. They said that DVCon gives them
a lot of exposure to the verification community and they
counted 7 new exhibitors this year.
- From the program, it appears that DVcon heavily favored Synopsys
System Verilog over Cadence Specman "e". While they're both
commonly used verification languages, DVcon'12 had plenty of
panels, papers, and tutorials focused on UVM with System Verilog,
but DVcon'12 had only 1 paper on "e" -- and it was on how to
migrate from Specman "e" to System Verilog.
- The UVM tutorial sold out again this year. I guess people
realized that it's actually hard to do.
All of the vendors above, and Forte, plan to be at DVcon'13 next year.
---- ---- ---- ---- ---- ---- ----
NASCUG'12: North American SystemC User Group Meeting
Tor Jeremiassen of TI acted as host & presenter.
Ed Sperling moderated a panel discussion on synergistic opportunities
for new SystemC-related standards activities in the context of the
merger of OSCI and Accellera. Panelists were Mike Meredith (Forte),
Tom Alsop (Intel), David Black (Doulos), and Ambar Sarkar (Paradigm).
There were about 70 people at the meeting/panel.
Tom Alsop discussed extension of UVM-like verification methodologies
to work within SystemC and the emergence of SystemC as a design language
using HLS.
Ambar Sarkar discussed the applicability of the UCIS work to
verification in SystemC.
David Black discussed the re-invigoration of the SystemC verification
working group under Jerome Cornet of ST's leadership and the potential
for coordination between that activity and the UCIS and UVM activity.
Mike Meredith discussed the increasing importance of design using HLS as
a SystemC use model and the impact that is expected to have on verification
activities. He also mentioned an initiative to coordinate the analog,
mixed-signal activities currently underway in the SystemC AMS working group
under Martin Barnasconi of NXP and in the Verilog AMS technical subcommittee
under Sri Chandrasekaran of Freescale.
C++11:
Another interesting talk in the NASCUG user group was David Black's
discussion of features in the new C++ standard, ISO/IEC 14882:2011, more
commonly known as C++11. Published last October, C++11 is the first
major revision of the standard since 1988. David speculated on a number
of ways the new standard could be used to reduce verbosity of SystemC
and improve its performance.
Sushil Mellon (U Penn) discussed his research into the applicability of
SystemC as a multi-core programming language for software. His results
lead to the conclusion that SystemC is a better hardware language than
it is a software language.
SW perspective:
"Industry Leaders" panel moderated by JL Gray (Verilab) -- The most
interesting elements of the panel came from Victoria Coleman (VP,
Emerging Platforms at Nokia) who brought a software perspective to the
discussion. She bemoaned the difficulty of verifying and debugging
the deep stack of software and hardware components that make up a
modern electronic system. She identified the "almost complete lack" of
tools to address these issues as a key problem in system design and,
to the dismay of the largely electronics/EDA oriented audience, offered
assurance that there was a sufficient willingness to pay for such tools
to make them an significant commercial opportunity.
- Brett Cline
Forte Design Systems Boston, MA
Editor's Note: I also heard a funny rumor that Jasper had a lunch
where, oddly, the ARM guy told the DVcon attendees how the Jasper
tool could *not* be used on the Cortex A15!? Not? Oops! - John
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