( ESNUG 494 Item 3 ) -------------------------------------------- [10/20/11]
Subject: Reader warns that you can't tweak Analog Rails tool results
> Analog Rails - Demonstrated a very tight link between schematic entry
> and layout placement. Both their schematic entry and layout tools are
> custom products but read and write out to OA. Various constraints
> can be placed on the schematic and these are reflected in the layout
> placement. The layout parasitics are then directly back annotated onto
> the schematic for simulation without having to go through the whole
> design, placement, extraction flow; which is one of the largest issues
> when you get to smaller geometries in analog design. This is quite a
> radical change in thinking but seems to deserve attention.
>
> - Chris Geen of Analog Devices, Inc.
> http://deepchip.com/items/dac11-08.html
From: [ The Cheshire Cat ]
Hi, John,
Anonymous please!
The Analog Rails tool presented at DAC 2011 is their first version were
everything finally works, the placer and the router.
This is not a tool for an average user, and not one for "architecture
exploration" either. Due to the fact that it's "correct-by-construction"
PnR for devices, all is controlled by Cliff's opinion about how things
have to be.
The user has no power to alter any layout after the fact, within the
Analog Rails environment. If you take it out to modify it, all liaison
between schematic, simulation and layout is gone.
In Analog Rails you can play in schematics but not in layout. Pretty much
the same concept as the original GDT from Mentor Graphics, 20 years ago.
(For some of you old enough to remember this is "single pass design", as
advertised a few years ago by a company called Monterey. They developed
the concept for digital. Analog Rails is the analog version.)
You enter the inputs and the Analog Rail tool decides for you everything
else. The placer is a topological implementation of the schematic, so if
your box has a different shape in layout, tough luck!
The router is GRIDDED but not at the process level (e.g. 0.1 microns), an
arbitrary grid to make the routes far away and non-interfering to each
other... Even if wrong, the user cannot modify it. No real process
knowledge, if you do 0.25, 0.18 or 40 nm, the routes will look and feel
the same... No electromigration or IR drop knowledge, but it can be
driven from schematics as WIDTHS.
There is one place where the Analog Rails tool can thrive: repeated designs
in similar processes or in versions of the same circuit. Some call this
derivative. Once you spend the time and effort to define an architecture
for an analog circuit, let's say a PLL, you get the layout done and it
is "good enough", you can easily generate all the versions of the PLL that
have the same devices but different sizes or similar process constraints.
So instead of having a team of people generating all these PLL versions,
you can have one expert and the Analog Rails tool for it.
However to get to that first version PLL is not trivial.
Also, it doesn't read process constraints from a PDK.
Until the Analog Rails tool allows users to make total or incremental
changes at device placement level, routing level, and ECO level; it is
not a main stream tool to use.
- [ The Cheshire Cat ]
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