( ESNUG 493 Item 1 ) -------------------------------------------- [09/15/11]

Subject: Gary Smith's study on IP Reuse in SoC designs

From the John Cooley DAC'11 Headaches Panel, Gary Smith gives his study
on IP Reuse in SoC designs, 1+ million gate blocks, OMAP, platform design,
statistics on IP sources of in-house vs. fab vs. other 3rd party IP, ARM,
Synopsys DesignWare, statistics on the biggest IP headaches, statistics
on design data management.



    Video of the Cooley DAC 2011 Headaches Panel on June 6th, 2011

Join    Index    Next->Item






   
 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)