( ESNUG 492 Item 6 ) -------------------------------------------- [06/06/11]
From: John Cooley <jcooley=user domain=zeroskew not mom>
Subject: The edgy questions for today's DAC headaches panel at 3:30
As promised, here's all the edgy questions that were submitted for
today's "Headaches" panel at 3:30 this afternoon at DAC.
Panelists:
- Gary Smith, EDA industry analyst
- David Genzer, Dir of IC design, Biotronik
- Jim Hogan, EDA investor
- Trent McConaghy, CSO, Solido Design
- Shiv Sikand, VP Eng, IC Manage
Date/Time: Monday, June 6, 3:30-4:30 pm
Location: DAC meeting room 25A
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Gary -- Do you just make shit up?
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Ask Gary how he makes money.
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Why does Synopsys hate Gary so much?
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Smith: What was the wrongest prediction you have ever made?
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To Jim, why do VC firms avoid EDA?
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For Hogan: what good ideas are you glad you did not invest in?
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What's Lucio's best current investment? His worst?
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What happened to Andy Betelchsteim? Why did he stop investing in EDA?
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Ask Hogan or Smith how Aart has poisoned the EDA start-up ecosystem.
Returns used to be 10x revenue. Now they're 2x or 3x for start-ups.
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Does Jim think Apache is going to IPO? If not, who's going to buy
them and for how much? Would he invest in Apache?
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Jim, what's the most disappointing investment you ever made in EDA?
What's the worst investment anyone has ever made in EDA?
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Ask Shiv why his company only has a part-time CEO? Why is his CEO even
in EDA when he makes 100x more $$$ on web security? Why should EDA users
buy from a CEO who sees EDA only as a side hobby?
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What's IC Manage's exit strategy?
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Q: How can you be absolutely certain that IP is verified and validated.
If we have to reverify, most of the value of IP is lost.
(think space or medical applications)
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Is anyone working towards a standard which would allow for stacking of
a piece of programmable logic on top of a custom IC?
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Process variation analysis is still a matter of trust and assumption
in most major IC houses. A foundry provides models you assume and
trust to be accurate, with variation metrics based on "hoped for"
distributions for real world occurrence, and statistical seed selection
algorithms for limiting simulation runs.
This is made even more difficult by the number of recipes a fab will
try to squeeze out that last bit of speed/leakage improvement. And
all this with tools little better than circuit simulators and in-house
table collection/statistical analysis scripts.
At best, you can only really hope to identify gross potential problems.
Why bother?
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How portable is my varation-aware design? If I design for TSMC, do I
have to start all over with Globalfoundries?
How does this impact second sourcing?
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Seems there is a continual broadening gap in terms of what most of
the wafer foundries can supply in terms of accurate SPICE and LPE models
and the higher order models built from them. How specifically can EDA
fix this when the foundries can't even model these effects at the
device level?
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How do the problems differ for 3rd party IP vs. internally-developed IP?
What is a DM company doing on an IP reuse panel? Are you making EDA tools?
What do they have to do to differently make your own IP work?
Are EDA companies afraid of IP reuse because it will hinder future sales
of design tools?
When an IP is reused multiple times in different chips, there will be
conflicting feedback to your in-house design team about how to improve
the next rev. Won't this customization negate the original intent of
reusable IP?
Who does IP help/hurt the most? The big companies or start-ups?
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How to best handle the "connectorization" of IP to enable simultaneous
handling of IP protocols coming from multiple IP supplier?
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I come from Product Lifecycle Management background primarily being used
from consumer electronics to automotive. Why does IC design not adopt the
best practices from PLM industry? Is the process of IC design really
different than any other design process?
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Why do we spend so much time analyzing variability and go through hoops
to find the right analysis, design techniques and sizing -- instead of
designing processes or materials to be invariable (so to speak) and
better controlling temp and voltage to begin with? Laws of physics
answers are not allowed.
Many want the benefit of IP reuse but do not want to invest in proper
re-use discipline like complete definition and adherence to simple
rules and documentation? IP reuse is not an afterthought but is an
intent and a long term commitment. What do you see as must-dos for
IP reuse? Give us some horror stories or best practice examples.
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Here are Solido questions
1. What makes variation rank #1 area needing focus in IC design? For
what design type and what nodes do you really need variation tools?
2. Can't you just guard band and blow out area to deal with variability?
Can't you already do Monte Carlo in the simulators?
3. What do variation tools do for PVT and Monte Carlo analysis that you
can't already do with SPICE simulation today?
4. When should variation analysis be done at the true SPICE level versus
the FastSPICE level?
5. What is a methodology for designing memory chips to 6-sigma?
6. How are layout-dependent effects handled pre-layout?
7. Which companies are offering which variation products for custom IC
design? How do they stack up?
8. We just design to PVT corners. Why would we do Monte Carlo?
9. What?s the responsibility of the foundry vs. the designer for variation?
How does TSMC handle variation in their reference flow?
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What is your opinion about the top issue in IP reuse, and why your company
provides the best solution?
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IP and EDA companies need to make IP seem simple to just connect stuff up
like legos and do a quick check that the interface is good and then you
are done! Why don't they do this????
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With so many analog acceleration/automation tools designed to mmitigate
process effects, why are they not more commonly adopted?
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Would you think there is value in putting FPGA Fabric within an SoC to
download different type of IP Solutions in it?
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How does one handle leakage power variation as it is significantly
different depending on the state of the design? If you look at a .lib
file, you will find it scary that the leakage power can vary by as
much 3x - 4x depending on the state of a gate.
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I have a couple questions these vendors have never been able to answer:
- I have 20 years worth of design files across hundreds of designs in a
variety of different file formats, different tool formats, and at
different nodes. How will you work with my existing data and the
undocumented variants?
- We are constantly trying to update our tool flows and design methods.
I will not be locked into a single vendor solution, but will replace
portions of my flow with best in class tools. How will you keep up with
the changing tool environment across multiple vendors?
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You could certainly ask them how they see the entry by Altera (Avalon
purchase) and Xilinx (Omiino purchase) is viewed? Will this trend
continue?
Similarly
You could ask how AMCC buying TPACK to aggregate business in FPGAs
till they can generate enough business to justify an ASSP is viewed?
Will this trend continue?
Is this really the first in a series of ASSP providers becoming
essentially complex IP providers via say Altera Hardcopy?
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With more customization of MOS technologies (strained channels, high-K
dielectrics, 3d channel shaping, and now even tri-gate structures being
discussed), do you not see the need for improvements in models?
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As for IP reuse, do you see ARM's AMBA as a de facto interface standard?
If so, how long will it continue to be? Do you see ARM's dominance being
threatened by new bus standards from AMD, Intel(Atom, Larrabee), or NVidia?
How serious do you take initiatives from these competitors?
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To SOLIDO GUY:
Which fab do you feel has done the most for enabling variation analysis,
or enabling your trust in the quality of your variation analysis? What
do you see as their greatest deficiencies?
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For variation in custom IC designs: How about using semi-custom techniques
like STA with Xtalk in custom-designs?
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Are long surviving IPs good for the end user or bad? Even INTEL's CPU IPs
are turning into self-killers. Will this happen to ARM also?
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How is the ESL space for IP business harvesting - Jim should know all
about it thru AutoESL.. Is this over hyped ?
There is still no genuine system level component synthesis from ESL-EDA
companies.. When can we synthesize say a full tablet ?
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Here is my question to IP vendors:
License fees often decrease over the number of designs that use the IP.
When several design teams within same company are planning to use the same
IP block, their "make" vs "buy" decision is biased because you never know
upfront which one will start first (and therefore who will pay the big
ticket).
Subscription models are even worse because they may result in one design
supporting the majority of the cost of one given IP block.
There is no easy way to fan-out the cost of a given IP on different design
teams.
Is that a barrier to IP reuse and how can the IP vendors help address this
problem ?
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Aimed mostly at Biotronik:
All IP customers want high reliability in the IP they purchase. What
do you do to "guarantee" the reliability of IP for "mission critical"
applications, such as implanted medical devices?
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Questions:
(1) Some engineers believe that IP is almost worthless without
accompanying verification IP. Do you agree?
(2) Does the IP come with OVM/UVM verification IP?
(3) How do customers know the quality of the verification IP?
(4) How much confidence can we have in multi-clock IP and why?
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Would fabless companies like full contour resist models from the Foundries
to further optimize their designs?
Critical Area Analysis (CAA) models are essentially useless in the
prediction of yield. Why do EDA companies do them?
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Why did Ivan Pesic's Simucad fail?
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BTW - you have anybody from Cadence on this panel?
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