( ESNUG 491 Item 7 ) -------------------------------------------- [05/12/11]
From: [ The Man in the Iron Mask ]
Subject: A DVclub case-study of IP and assertions in Zocalo Zazz Visual SVA
Hi John,
Please keep me anon.
I went to a DVClub lunch meeting in Milpitas with 120 engineers on April 26
where two companies presented case studies. Here's my 2nd of two reports.
Eric Deal is a consultant at Cyclic Design talked about the benefits of
using assertions to reduce the time to identify and debug failures, improve
design and verification team communication, document design behavior, detect
unobservable faults, and easing the integration of reused IP modules.
Eric said OVL assertions were simple, but pretty inflexible. In contrast,
he liked System Verilog Assertions (SVA) because they were more flexible,
had a concise syntax and were still powerful. He said SVA had a "clean
way" to create simple assertions.
SVA had its own drawbacks; it was difficult to construct anything beyond
simple assertions. When you tried to create moderately complex assertions,
they often triggered incorrectly, so he felt the time to debug them wasn't
worth the effort to create them.
Zocalo asked him to give them feedback on Zazz Visual SVA, which lets you
create complex assertions without needing to be an expert on SVA syntax.
Zazz also debugs assertions as you create them. Eric said this debugging
of assertions prior to using them is why many companies use predefined
assertion templates like OVL.
Zocalo Zazz Visual SVA
Zazz represents assertions graphically in a 2-dimension canvas showing
temporal view and concurrency, which makes it easy to create assertions
and understand the relationships between the operators.
Eric also showed how Zazz Visual SVA also helped in creating structurally
and syntactically correct SVAs:
Finally, Eric showed how Zazz Visual SVA helped in debugging Assertions
by creating a constrained-random testbench around each assertion.
Eric said that the assertions he created with Zazz improved his internal
verification and debug by identifying the time and location of errors in
simulation and identifying corner-case errors. He also said the
assertions improved his customer's experience when using Cyclic's IP.
Example #1: FPGA Regression of Cyclic's ECC IP.
Eric used the FPGA to run billions of correction operations. When a test
failed, he would replay the vector in simulation, and in almost cases, a
Zocalo assertion would fire to indicating the cause of the failure.
Example #2: Assertions in IP
Cyclic Design's BCH ECC IP supports different maximum ECC levels. One
customer configured their application logic for a 60-bit BCH ECC IP and
ran the included testbench, which showed an error. When the customer
called him, Eric instructed him to enable the assertions. 3 unrelated
assertions immediately flagged the problem: the testbench was running a
test using 64-bit ECC. Eric has gotten feedback from other customers on
how having the Zocalo assertions in the IP helped them flag violations
when verifying the IP in their design.
- [ The Man in the Iron Mask ]
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