( ESNUG 490 Item 7 ) -------------------------------------------- [04/06/11]
From: John Weiland <john.weiland=user abraxascorp got calm>
Subject: Magma SiliconSmart, Nangate, Synopsys Cadabra, Prolific, Altos
Hi, John,
Magma sells a suite of cell characterization tools called SiliconSmart
whatever, which they claim are number 1 in this segment. Their basic
SiliconSmart tool does characterization of standard cells and IO, and now
comes with their FineSim SPICE simulator embedded and hence faster than
using an outside simulator. Magma also has a tool called SiliconSmart
Signoff, which adds noise and power modeling which are missing in their
basic tool. They also sell SiliconSmart DFM, which characterizes both
systemic and random process variation in cells so that margins for
On Chip Variation (OCV) can be eliminated. They say that using the real
variation in the SSTA (statistical static timing analysis) models allows
the user to squeeze more speed out of a given process (that makes sense).
Nangate sells tools for library generation and characterization. One tool
generates libraries using synthesis and compaction. A second characterizes
libraries and produces models in formats like Liberty, Verilog, LEF, GDSII,
etc. A third tool analyzes and compares Synopsys Liberty (.lib) files.
Their Mega Libraries contain 10,000 to 50,000 cells and a huge variety of
drive strengths, including multi-Vt and long gate versions of cells. They
say long gate cells are better than low Vt cells at low supply voltages.
Nangate claims the large variety of cells can result in up to a 14% speed
increase for some designs. Mega Libraries for TSMC 65 nm & 45 nm are new.
Synopsys sells Cadabra, which they got when they bought Numerical, for
library generation (SPICE-netlist-to-layout). The tool is OPC aware and
utilizes unused space to increase yield. Liberty NCX (replacing NanoChar)
for library characterization, which works with HSPICE.
Prolific sells ProGenesis, which generates libraries. It accepts a SPICE
netlist and produces a layout using both generators and synthesis (most
competitors use one or the other). They claim it has been used to produce
a complete 20 nm library.
Cadence sells the Encounter Library Characterizer. It supports both ECSM
(Cadence) and CCS (Synopsys) advanced delay models, power models, signal
integrity and statistical analyses. It automatically generates vectors or
accepts user vectors, and has automatic recognition of complex gates.
Z Circuit Automation sells tools for library characterization, including
differential inputs and dynamic logic, and they support statistical timing,
CCS and ECSM. They say they can characterize a flip flop in 1 minute and
are proud of the speed and parallelism of their methods. They can also
characterize memories because their tool is built on a general purpose
waveform analyzer so it scales well to large cells. Z Circuit says their
memory characterization is now 10X faster due to netlist reductions and
they can do very large memories. They also sell a tool to check libraries.
The input is a SPICE model, constraints, a .lib file and Verilog models.
It checks for consistency between the models and also does basic sanity
checks and new for this year it has a rule based checker.
Altos has a tool for library characterization. They sell a tool called
Liberate LV that checks Liberty (.lib), Verilog and Vital models versus
SPICE. It confirms timing, noise and power data, and does data consistency
checks (e.g. does delay increase monotonically with load). They also sell
a tool called Liberate MX for characterizing memories and custom macro
blocks that uses "dynamic partitioning" and does not require pattern
matching, so it can work on a wide variety of cell types. They say it is
up to 4X faster than HSPICE.
Editor's Note: Altos also just recently got integrated into Berkeley
Analog FastSPICE claiming it now "delivers 5x-10x faster I/O cell
characterization" including device noise & parasitics "with nanometer
SPICE accuracy". In addition, Altos is the only EDA company to win
the 2010 Texas Instruments 2010 Supplier Excellence Award. - John C.
Legend Design has a tool for characterizing libraries called "CharFlo-Cell!"
(yes, the exclamation point is part of the name). They also sell Model
Diagnoser, which is designed to diagnose mismatches between your .lib
functional model and the actual layout via simulation, and they say they
can actually fix your .lib model if it is wrong. Input is a .lib file,
SPICE model and netlist, and the output is a correct .lib file and reports.
Library Technologies sells tools for characterizing std cells, memories and
full custom blocks, but they emphasize the use of this within the larger
goal of optimizing cells for timing, power, and yield rather than going
head-to-head against the multitude in the characterization business. They
provide optimized transistor-level netlists for cells for these purposes,
but do not do the layout. Lib Tech generates best and worst case models
for each individual cell. I would think this would add pessimism to the
analysis but they say it helps avoid SSTA, which is also very pessimistic.
They also use their characterization tool to create libraries for their
power simulator, which they claim is more accurate than other gate level
power simulators because it understands what is going on in internal nodes.
Lib Tech has a tool that checks libraries but it is not sold separately.
They also have a tool that creates cells with new drive strengths (no new
logic functions) in order to achieve timing closure. The tool outputs a
netlist but the user must still create the layout. Last year they claimed
this can reduce gate count by 10% and critical path delay by 30%. This
year they claimed up to a 2X speed improvement.
- John Weiland
Abraxas Corp. Columbia, MD
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