( ESNUG 490 Item 4 ) -------------------------------------------- [03/31/11]
Subject: Well, our Atoptech Aprisa correlation with PT-SI was excellent
> We ran into some very poor correlation between DC and ATopTech P&R.
> The differences we saw were 200% off on RC values for long nets, and
> 100's of psecs of difference in STA on 500 psec paths, i.e. ~20% off.
>
> - http://www.DeepChip.com/items/0487-01.html
From: [ Hello Kitty ]
Hi, John,
Anon please.
We switched to Atoptech last April. We're appx 6 weeks away from taping
out our first two 40 nm chips with Aprisa (AP). I don't have a lot of time
right now to provide quantitative data but I will try to hit the key points.
We'll provide more details after tape-out:
1. The two chips are apx 40 M gates each.
2. They are assembled using a top down methodology. Sub-blocks range
from 8 to 10 M gates in size.
3. Correlation with PT-SI is excellent. When AP says it meets timing,
it does. There are no surprises running PT-SI.
4. We have done "one" ECO at the block level to fix a 13 psec setup
violation. This is very important to us as it eliminates the
manual ECO's cycle.
4. AP is inherently DRC clean. The numbers of DRC errors in each
sub-block ranged from 0 to 5. It also produces litho-clean results.
5. AP is fast. We can go from RTL to a GDS ready in two weeks for
any of our 8-10 M gates sub-blocks.
As mentioned above, we will provide quantitative data after our tap-outs(s).
I'll wrap up saying we are very pleased with the Atoptech results so far.
- [ Hello Kitty ]
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