( ESNUG 488 Item 10 ) ------------------------------------------- [03/25/11]

Subject: (ESNUG 488 #6)  User eval confirms Mentor CatapultC does SystemC

> I must now note for a company that told us in DeepChip at every turn that
> "ANSI-C is all you'll ever need" and "SystemC is just low-level RTL",
> Mentor Graphics sure seems to have found religion very recently.  Even
> CatapultC announced a SystemC version some time last year -- though it
> seems to be struggling in the market.
>
>     - Brett Cline
>       aka "the SystemC poster boy"
>       Forte Design Systems                       Acton, MA


From: [ One of the Seven Samurai ]

Hi, John,

Sorry I must be anonymous.

We did an eval of Mentor's SystemC support.  CatapultC does SystemC.

We wanted our test to be rigorous, so we used an existing scaler design.
Our scaler was implemented in 90 nm technology.  It does down and up
scaling of frames from 1x1 to 1024x1024 pixels; each pixel has four
8-bit components.  The scale factors are configurable, with an integrated
640 pixel line buffer.

What we wanted and what we found:

  1. Broad range SystemC language support.

     Result: Catapult met our requirement.  Our evaluation design was
     a scaler from a former project, so we had legacy SystemC code.  We
     had no problems adapting our SystemC coding style and verification
     flow for Catapult.  Only a few changes were necessary, and Mentor
     helped us resolved them within 3-4 days.

  2. In our graphic designs, our blocks are connected via back stalling
     point-to-point interfaces.  We needed basic point-to-point pipeline
     stages with 1 input and 1 output, as well as arbiters, routers and
     crossbars.  Modeling these in RTL is very error prone.  We wanted
     to investigate if sc_fifo interfaces were synthesizable by Catapult
     in such point-to-point frameworks, so we modeled our point-to-point
     infrastructures in SystemC.

     Result: Catapult successfully synthesized the examples as modeled.

  3. The implementation of the arbiters and routers should meet our max
     throughput of 1 pixel per clock cycle.  In most cases, it was
     essential to have an initiation interval of 1.

     Result: Catapult met our requirement.

  4. Exact translation of SystemC fixed point datatypes, including the
     quantization and overflow modes, as defined in the Standard SystemC
     Language Reference Manual.

     Result: Catapult met our requirement.

QOR:

To assess Catapult C's results in an accurate context, we replaced our
production scaler with Catapult's RTL.  We were able to reuse our original
set up and scripts.  Catapult generated RTL with an area of approximately
45,000 um2 logic area (without RAM).  Catapult's RTL also met our 160 MHz
clock speed requirement.  This met our prior design's QoR.

Verification:

We used Mentor's automated SC Verify flow for going from behavior to RTL
verification with Cadence NC-Sim.  We verified the correctness of the
interface behavior and the fixed point arithmetic with RTL regressions
for several scaling configurations and randomized timing at point-to-point
inputs/outputs.  We measured the functional coverage of each external and
internal point-to-point interface using PSL.  Since we had previously
implemented our design, our reference point was well-verified RTL.

We also liked Catapult's charts for graphical analysis of HLS synthesis
results and back annotation to C code.

    - [ One of the Seven Samurai ]
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