( ESNUG 486 Item 10 ) ------------------------------------------- [10/08/10]
From: Scott Taft <scott.taft=user domain=foveon got mom>
Subject: Clever partitioning with IC Manage and Synopsys Custom Designer
Hi, John,
We used IC Manage GDP with Synopsys Custom Designer to tape out our next
generation .18 um, 46 M pixel direct image sensor. We used GDP with the
Schematic Editor (SE), HSPICE, HSIM, CustomSim XA and Custom Designer
Layout Editor (LE) files.
WORKSPACES
With IC Manage's Global Design Platform each designer creates a "workspace"
which is a personal copy of the hierarchical design data to use. Every
designer can have multiple workspaces and keep direct control over what
file revisions they want to sync to.
They can each save off views that other users can access and (if they want)
reuse for similar blocks. Sometimes we have libs which we don't want anyone
having write access to, so we configure workspaces for read-only access.
We have multiple groups that access IC Manage. Below is how they each use
GDP workspaces.
1. Our chip design group
- Front end designer: CD Schematic and symbol views, HSPICE/HSIM
state files, text files
- Layout designer: CD layout view, abstract view, text files
For example, one of our layout designers might have a workspace
associated with getting their block to be LVS/DRC clean. GDP's
library manager looks just like the Custom Designer (CD) library
manager, but adds design data management menu items like check-in
check-out and version history as well as icons indicating version
number and check-out status.
2. Our pixel design group
Our pixel design group not only designs the pixel, but they are also
involved with creating process control monitoring (PCM) structures.
The pixel group also verifies that each pixel is placed correctly
in the top-level design.
3. Management
Various managers can set-up a customized workspace in about 5 minutes
to do a design review on a design in progress or reference back to
a design that was taped out, then discard the workspace.
MANAGING DESIGN DATA HANDOFFS
Our design process involves a lot of handoffs between team members. Our
top-level architect defines the major blocks, then we assign lead engineers
to each block. As the engineers get close to a finished design with CD SE,
they hand it to the CD LE designer in an iterative process with the design
engineer, then use the final design for that block to do a final parasitic
extracted simulation in HSPICE.
We encourage our designers to use GDP to check in their work often,
sometimes multiple check-ins a day, so that we can record milestones, and
so other engineers can use the information (e.g. input and output data) for
their own blocks. Typically a designer will check in their new version but
and leave the one they are working on checked out, because they don't want
others to grab it. This gives them better control over their designs
because they don't need to worry about having their data changed under them.
Below is data on IC Manage's check-in/check-out performance. Our entire
design group is in Santa Clara, so I can only comment on IC Manage's
performance over our local network.
Block size Check-in time Check-out time File size
20 M arrayed instances 1 sec 1 sec 6 MB
6 M shapes 7 secs 6 secs 133 MB
It's worth noting that this performance is so fast that no users have ever
complained nor have they sought ways around the system. 100% of our
designs are managed.
ECO's
With IC Manage, the fix process binds the check-in event to the actual ECO
in both the IC Manage database and the bug tracking database, so we can
easily track design changes. IC Manage also makes it easy to trace back a
design to an earlier working version to help better understand how some
bugs are introduced.
USING GDP WITH OUR THIRD PARTY IP
Our image sensor is mostly an analog/mixed signal design that is designed
in house, we also have a few digital blocks using standard cells, plus some
3rd party blocks such as PLLs and LVDS. Our 3rd party IP providers don't
have a direct connection to our IC Manage database, so they give us data
dumps that we check-in as revisions. The nice thing is that everyone can
access the IP provider's data once it's in house via IC Manage's Library
Manager -- we just check their data into IC Manage and run LVS and DRC on
the IP. As they give us more data and can track the changes.
USING GDP FOR DERIVATIVE DESIGNS
When we clone or integrate a design with GDP, we take a library and branch
it off to derive a version of the chip, as follows:
- We take 1 main branch of a library and choose a point in time when the
design is final for a specific chip and branch it off as a separate
design tree.
- We can continue designing with the original baseline branch.
- If we change a block on the branched design, we can easily feed it back
to the original development tree because GDP maintains a bi-directional
integration path between the parent and child. The IC Manage software
automatically tracks the changes between branches so we don't need to do
diffs and merges.
Typically, we use IC Manage to branch the final design off as separate
design tree just before tapeout as an read-only archive. We can do
variations to that chip later, but the base libraries stay the same, so we
keep a clean snapshot while we develop another design.
TIPS ON USING IC MANAGE'S PROJECT MANAGER TO ORGANIZE DESIGN PROJECTS
We found that depending on how we partitioned our design, we could end up
with problems down the road. I can share some tips on how to assess the
best way to break down your project for design management purposes.
When we first got IC Manage (back in 2006 - we've been a happy customer for
several years now), we didn't have a strong understanding of how to use it
effectively. So we took a month to experiment with it.
IC Manage gives you flexibility in creating design categories and projects.
We had multiple design engineers create a sandbox to play around with the
tool -- setting up test partitioning and going through some typical design
cycles -- before we used it in production. Now that we have figured out
how to best structure our project, it only takes us a few hours to set
GDP up for new designs.
You need to pay close attention to how to partition the design when
creating the specific libraries in IC Manage. We found it helpful to look
at where the data comes from, how it's used, and how it changes. Here is
an example of the partitioning schemes we found effective:
Technology library
Standard Cell library
Other external IP libraries
Pad library
Top level library
Lower level cells library
We choose to split our designs this way because our lower level cells tend
to change a lot but are reused by the top level ones. This way we can have
1 top level library using the lower level libraries. In the same way, each
of the standard cell libraries can be used by different blocks.
You can create different projects inside IC Manage. We create one project
just for standard cells -- only standard cells exist in that project,
because they are used by our different designs within our company and are
not revised very often. These reusable libs can then be easily referenced
from chip design projects.
IC Manage structures the data in a human understandable GUI. Each project
is a higher level construct and can contain multiple libraries. Some are
specific to that particular design and some are references to other data,
like pad libraries and standard cells.
If we replicated a standard cell library over multiple chip designs, there
is potentially lots of redundant data, which doesn't change very often.
With IC Manage, our designers don't have to replicate data as we have a
single item that we can reference -- we don't need new copies for each chip
we create. We can hard code the references to a specific revision of a
chip taped out with those standards cells, and GDP points to that revision.
So a revision to the standard cell doesn't affect existing designs, just
the new ones that we choose to update. This feature also gives us the
ability to determine exactly which version of a particular block has been
used in a specific tape-out without having to store it in a spreadsheet
somewhere.
I can't think of any drawbacks or improvements right now. IC Manage's
biggest strengths are the tight revision control, easy configuration
management and ease of design archiving. IC Manage has been willing to
work with us a lot. The R&D support has been wonderful, which means a lot;
they always get back to us within a day, and most workarounds are found
within 2 days.
- Scott Taft
Foveon, Inc. Santa Clara, CA
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