( ESNUG 486 Item 7 ) -------------------------------------------- [07/30/10]
Subject: ( ESNUG 479 #4 ) "How many companies are actually using HLS?"
> We recently ran a blind worldwide survey on what companies see as their
> primary reasons for using ANSI-C/C++/SystemC-to-RTL synthesis. A total
> of 820 engineers responded ... Almost 2/3rds (64%) recognized that high
> level synthesis will get to RTL code faster.
>
> - Shawn McCloud
> Mentor Graphics Wilsonville, OR
From: Shawn McCloud <shawn_mccloud=user domain=mentor hot calm>
Hi again John,
Mentor's Catapult group ran its 2nd annual blind worldwide survey on High
Level Synthesis (HLS). This time a total of 1,076 engineers responded.
We found two interesting results to share with your readers. One on HLS
adoption and the other on HLS language preferences. An interesting question
we asked this year was:
"Does your organization plan to implement High Level Synthesis
(SystemC/C/C++ to RTL) in 2010?"
No : ############ 37%
Don't know : ########## 29%
Yes : ######## 23%
Already have HLS : #### 12%
12 percent of organizations said they had at least initially implemented
high level synthesis to generate their RTL code. By the end of 2010, more
than 1 in 3 design organizations expected to use HLS tools in-house. It's
important to note that this is not 1 in 3 engineers, but rather 1 in 3
"organizations," that say they will be using HLS. Even so, it's a healthy
interest!
There has been a lot of discussion in your forum about HLS languages and
specifically about C++ vs. SystemC. But SystemC is based on C++, so the
real question is the one of abstraction, that is how much information one
needs to put in the source description to fully specify the behavior and
meet the design goals in terms of area, performance and power.
To make an analogy, Verilog is a language supporting multiple abstraction
levels. While it was first adopted for gate-level simulation, designers
eventually migrated to the higher RTL models that abstracted away the
gate-level timing, and relied on synthesis tools to manage the timing for
them. High Level Synthesis improves designer productivity by abstracting
away specific implementation details. So we used this survey to focus on
the question of timing abstraction.
"What is the best language for high level synthesis?"
Don't know : ########### 33%
Untimed (ANSI C/C++, SystemC-TLM) : ########## 30%
Timed (SystemC-cycle accurate) : ######## 25%
Matlab : #### 12%
This survey shows an interesting fact: 30 percent of designers prefer
UNTIMED HLS language input, compared with 25% of designers that prefer TIMED
HLS language input. This makes sense in that both timed and untimed input
each have a specific purpose in helping to achieve full chip high level
synthesis.
- Timed (SystemC-cycle accurate) descriptions are applicable for the
kinds of control structures and complex bus interface protocols
typically found in SoCs. In addition, we have observed another
pattern from HLS users:
1. As some designers move up from RTL, cycle-accurate models offer
an intermediate abstraction they can easily learn and relate to.
2. The design can put explicit timing in the source and code more
details in the model to gain more direct control over the
generated result. In this case, the designer is consciously
trading off abstraction for predictability and control.
- Untimed (C++, SystemC TLM) descriptions are ideally suited for
algorithmic designs, since designers do not have to worry about hard
coding clocks, concurrency and timing behavior directly in the source
but use HLS to insert this detail for them. Mentor's customers using
untimed descriptions have indicated that there are three main reasons
why they prefer the untimed models.
1. These untimed models are much easier to verify and maintain
because there are much fewer details in the source.
2. The untimed models are more generic and can be more easily
retargeted to different architectures across design goals and
silicon technology.
3. There is an enormous available legacy of untimed models. While
most of them may not be immediately synthesizable (for good QoR),
it takes designers less effort to get there from legacy models
than to develop new cycle-accurate models.
Mentor Graphics' Catapult C synthesis solution supports both pure C++ and
SystemC, offering a wide choice of modeling and synthesis options. Users
can choose the most appropriate abstraction level for their design needs:
cycle-accurate SystemC, transaction-level SystemC, and purely untimed C++.
And to help users make the most out of their ESL flow, Catapult tightly
links to Mentor Graphics' Vista Architect solution for SystemC modeling,
debug and analysis for a comprehensive ESL design, verification and
synthesis flow.
Additionally, as we observed in last year's survey (ESNUG 497 #4), when
people adopt HLS it is first and foremost to reduce the RTL verification
effort. This is why HLS tools must be architected from the ground up with
verification in mind, and this is why Mentor continues to invest R&D on the
link between HLS and verification. Higher abstraction is obviously one of
the keys, but it is not the only one. For instance, we have recently added
C++ code coverage and linting features to Catapult C. In an ASIC flow you
wouldn't freeze Verilog code until you reach sufficient coverage.
Similarly, you don't want to commit to your C++ code if it hasn't been
thoroughly tested and tagged as clean for synthesis. Catapult C's generated
RTL will not only match your input C code - it will help you ensure the C
code you match is correct. With a well architected HLS methodology, RTL
verification becomes automatic and predictable. As Slumdog Billionaire put
it in ESNUG 481 #7: I really like this functionality as it frees up my time
to do actual design. Doing unit level verification is really as simple as
coding C++. Once I got the design working, the unit level verification only
took 2 days."
- Shawn McCloud
Mentor Graphics Wilsonville, OR
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