( ESNUG 486 Item 3 ) -------------------------------------------- [10/26/10]
From: Jeff Dyck <jdyck=user domain=solidodesign got calm>
Subject: A Boston SNUG trip report from an analog engineer's point of view
Hi, John,
I recently attended the Boston SNUG and thought your readers might like my
trip report on it.
AART'S KEYNOTE - VIRTUALIZATION AND IP
Aart's keynote focused on accelerating SW development by virtualization.
His key points:
- Software complexity in modern products is increasing.
- Calendar time for software development is also increasing and is now
exceeding time for hardware development.
- In order to bring products to market faster, software development must
start much sooner using virtualization rather than waiting for the
hardware to be ready before developing the software.
- Variation-aware design was one of the top items requested by Synopsys'
customers for 28nm and 22nm designs.
- de Geus presented Synopsys' virtualization strategy by giving an
overview of their recent acquisitions in the space (e.g. CoWare,
VaST, Synfora).
- Synopsys has a heavy investment in IP design. I was surprised to hear
their recent acquisition of Virage Logic brought their IP designer
headcount to over 600 people.
FUTURE OF AMS VERIFICATION
Since I am a custom IC design tool developer focused on variation, the most
useful presentation to me was Warren Wong's "Future of AMS Verification."
Some of Wong's notable takes were:
- Parasitic reduction: Improving parasitic reduction technology is key
to reducing simulation times for larger, post-layout designs. This is
important because 1) designs are getting more complex, and 2) more
thorough post-layout simulation is becoming increasingly important at
smaller technology nodes.
- Proximity effects: There are increasing numbers of proximity effects
to account for at newer process nodes. Synopsys says they help
designers to analyze proximity effects in simulation. Wong mentioned
the need to enhance Synopsys' FastSPICE simulators (XA and HSIM) to
simulate proximity effects. I asked Wong what Synopsys' customers are
doing to prevent and debug proximity problems, to which he replied,
"If you have a problem, then you have a problem," and explained that
proximity problems recently cost one of their customers 6 months on a
single product.
- SPICE capacity problems: SPICE capacity is not currently keeping up
with design complexity, and this will be a growing problem over time.
- Modeling problems: Wong said there is a general lack of trust for
device models. He pointed to the need for automatic model generation
and verification. There are several start-up companies in this area,
and Wong suggested their technologies are not yet sufficiently proven.
- Mixed signal verification: This is now a must, and better support is
required.
- Assertions and coverage: The digital practices of using assertions
and measuring coverage need to be ported to analog design.
- Monte Carlo analysis: Wong highlighted several necessary enhancements
to statistical verification, including:
Monte Carlo accuracy needs to be improved, and better support is
needed for running over 1000 samples.
Monte Carlo is still not feasible for larger blocks (max. is
currently ~1M devices with FastSPICE).
Better sampling techniques are required. Despite some being
available in Synopsys products, Synopsys' customers still do not
understand the benefits and cannot verify their accuracy. New
sampling techniques need to be accuracy-aware to win designer
trust.
Design debugging needs to be improved. Monte Carlo analysis can
tell the designer when there is a problem, but provides little
insight into how to fix it. Wong referred to "hot spot"
detection as a needed enhancement.
Better Monte Carlo data mining and visualization GUI tools are
needed.
In Q&A, Wong also discussed the need for "extreme sampling,"
which drives samples in the tail regions in the output space, and
not the middle of the output distribution.
- Thermal gradients: Wong stated that although thermal gradient
problems have attracted recent academic and industry attention,
Synopsys' customers have not been asking for solutions. Synopsys'
first customer asked for a thermal gradient solution this year, so
this may now be increasing in importance to address.
SYNOPSYS CUSTOM DESIGNER DEMO
Fredrik Ivarsson demonstrated Synopsys Custom Designer. From his demo:
- Synopsys has built out all the core front-end components, including
schematic capture tool, a simulation environment, and a layout editor.
- In many ways, Custom Designer (CD) mimics Cadence Virtuoso to minimize
the designer's learning curve.
- CD has shortcuts designed to save designer time, such as the ability
to edit CDF parameters directly in the schematic, and advanced
schematic-driven layout capabilities.
- CD's simulation environment, SAE, includes basic features and seems
similar in scope to Cadence ADE L, plus a basic PVT corner tool and a
basic Monte Carlo tool. Ivarsson emphasized that SAE is open and is
easy to integrate third party simulators. Its post-processing
measurement options seem flexible, and it includes the ability to add
user-defined calculations and to integrate with third party
post-processing tools like Matlab in the loop. CD's simulation
environment is included with the schematic capture license.
- Synopsys has mandated use of Custom Designer for all of their 600+
internal IP designers and claims they have some external customers
as well now.
One of Synopsys' Custom Designer customers, Michael Wagner of Lantiq,
delivered an earlier session on how Lantiq deployed Custom Designer for use
with their 40 nm design flow. Wagner emphasized that they were able to
deploy CD quickly and with limited CAD resources.
HSPICE SIMULATOR ENHANCEMENTS
Synopsys highlighted their new simulator enhancements throughout the
sessions and offered a live demo of HSPICE. Some of Synopsys' key
announcements were:
- "Precision Parallel Technology," released the same week as Boston
SNUG, claims to deliver up to a 7x speedup on an 8 core machine.
- Claims HSPICE is nearly 2X as fast as it was on a single core 2 years
ago.
- Claims HSPICE's device capacity is 5x what it was 2 years ago and
can handle post-layout circuits with up to 10M devices.
- And claims that XA, Synopsys' new FastSPICE simulator, delivers
similar speed-ups to HSIM, but with near SPICE accuracy.
Boston SNUG 2010 has around 300 attendees. It was a good opportunity to
catch up on what Synopsys has been working on.
- Jeff Dyck
Solido DA Saskatoon, Canada
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