( ESNUG 485 Item 7 ) -------------------------------------------- [05/27/10]
From: Glenn Murphy <gmurphy=user domain=qualcomm got calm>
Subject: User says Solido speeds up Cadence Spectre variation design by 5X
Hi, John,
I ran a 2.5 month eval of Solido Variation Designer (VD) tools for custom
IC design in late 2009 and we purchased them earlier this year. Solido VD
bolts onto our Cadence Virtuoso Analog Design Environment (ADE) and Spectre.
Solido sped up our analysis by about 5x versus just using Cadence tools
(details below). Because Solido uses Spectre's simulation engine and full
foundry models (in our case TSMC models) for its analysis, their results
are identical to Spectre -- with zero degradation in accuracy.
Solido automates these primary steps, which I estimate reduces our typical
custom IC design time from 7 weeks down to 6 weeks, or by about 15%. It
1. Analyzed variation on performance, power, area and parametric yield.
2. Identified the most sensitive transistors that impact our specs.
3. Suggested fixes to our transistors.
4. Verified that our fixes brought the design back within spec.
In our typical design, some portion of the transistors will be sensitive to
variations, some as much as 20%. We use Solido VD to meet our performance
requirements over these variations and often to reduce the variation itself.
Solido VD is really a set of packages:
- Solido PVT+ for process corners in foundry model files (e.g. TT, FF,
SS, etc.) and variation caused by environmental conditions such as
voltage, temperature and load.
- Solido MC+ for Monte Carlo on mismatch and global random variations.
- Solido Prox+ for well proximity effects impact and minimizing guard
band area in layout.
I've used Solido to increase performance and parametric yield for both 45 nm
and 28 nm designs, as variations can also significantly impact performance
above 28 nm. I optimized my 45 nm designs with Solido, then translated the
designs into 28 nm for our next generation products; in this way I got a
jump start in analyzing the impact of the new process on my original design.
Capacity. We ran circuits of about 100 gates to circuits of about 3,000
gates. I never tested Solido's capacity above or below that range. Solido
claims their tool's full capacity is 100K devices.
SOLIDO VD AND CADENCE VIRTUOSO INTEGRATION:
We used Cadence Virtuoso ADE 5.1.41, plus 6.1.3.500.17
Learning Solido was so simple even a caveman could do it. It took me just
about 30 minutes sitting down with a VD AE to learn the basic use of the
tool for my design. Many tools claim to be easy to use and well integrated
into Cadence, but VD really was.
- All I had to do was add a "setenv SOLIDO_ENABLE 1" environment
variable to our Cadence project file and Solido showed up as a
separate menu option in Virtuoso ADE.
- Select Solido in the Virtuoso ADE menu, a Solido VD window opens.
- Solido uses the existing ADE state - which contains the setup of
our circuit's performance measurement and design variables - for
its analysis.
- Solido saves the Solido state and analysis data in files that reside
within the Cadence library manager cell view.
- We can see the sensitive devices Solido finds highlighted right on
our Cadence schematic.
- Solido also has integrated support for Platform LSF (load sharing
facility for simulation farms) and can use multiple CPUs.
I then spent several days using VD to evaluate previous designs. I was able
to find real design issues that have now been corrected in my last tape-out.
Specifically, I used their Prox+ well-proximity tool to analyze an existing
45 nm design and found that the well spacing for my NMOS and PMOS current
mirror devices caused excessive mismatch for my design. I then used Solido
to reduce my design's mismatch to an acceptable level.
SOLIDO PVT+
PVT+ works with Spectre to simultaneously simulate global variations of
foundry process corners (TT, FF, SS, FS, and SF) and environmental
conditions such as voltage, temperature, load, bias, etc. It follows up the
analysis with the standard Variation Designer "identify, fix and verify"
steps.
Before using PVT+, I used Virtuoso ADE with Ocean. Ocean is Cadence's batch
scripting language for running sets of simulations and compiling results
generated by Cadence simulators such as Spectre. I would normally run 27
corners; the chip had to work across all these conditions. I would
normally run these 3 variables at the following settings: SS/1.65VDC/+125,
TT/1.8VDC/+27, FF/1.98VDC/-40.
My normal method of analysis (before Solido) was to print a waveform showing
a circuit behavior over a particular corner. That method had many
limitations, time being the most problematic. It could take a day or so for
me just to get an Ocean script up and running. A simple thing like changing
a net name or adding a design variable meant I had to re-test my script.
Ocean scripts run sequentially, unless I wrote more elaborate code to run
them in parallel. This meant my 27 simulations ran on 27 machines, and the
results were in different directories instead of all being in one place.
After I ran the 27 simulations, I had to look through all the results and
manually determine which were the worst case corners, then try to identify
sensitive devices through a combination of intuition and trial and error.
Once I determined some fixes, I would rerun the Ocean script which kicked
off all 27 simulations again.
For some designs, I need to run 100's of corners. But even when I picked
only 27 corners it took time to get it right.
Solido PVT+ was very useful and I was able to setup and run PVT analysis
within a few minutes. As with Monte Carlo+, PVT+ uses the setup from my
current Virtuoso ADE state. To run a PVT corners simulation:
1. Selected "Project Setup"
2. A GUI popped up which listed all of the tabs, in a logical
sequence, required to run the PVT.
3. In this case, I stepped through "Specifications", "Environment"
followed by "Corners". PVT+ has other tabs like "device linking",
but I didn't use them initially.
PVT+ has a fairly intuitive user interface for interpreting the results:
- The naming of the tabs is similar to Cadence naming conventions
- The task sequencing layout
- Help menus are located next to most operations
- Descriptors (when you click an application within a package,
e.g. mismatch -- it will describe the function)
PVT+ gives you many ways to evaluate PVT data, e.g. I can establish specific
numeric limits for multiple design parameters and I can sort the PVT data
based on corner parameters. The approach they taught me:
- Identify. After simulating my corners, I save just the worst-case
for my design. Then I can sweep sets of linked devices together to
maintain similar sizing and to identify which are the most sensitive
to those worst-case corners.
- Fix. I can then review the list and sweep plots. Solido then
suggests the geometry fixes to implement for the sensitive
transistors to improve performance, e.g. current mismatch and
output amplitude.
- Verify. When I run each of my geometry changes, I can run for just
the worst-case corners without doing manual analysis. Once I'm
satisfied, I can run all 27 corners one last time and capture the
results for design review.
It's harder to do this manually because even with Ocean scripts I must
program each corner, and make sure that I set each parameter that I use in
the run. This can be painful since I must manually update my Ocean script
each time a parameter is changed. Regression tests are even more of a pain
since the simulation states aren't saved within the Ocean script. Then the
simulation is loaded and run. This takes more time and is more error prone.
PVT+ also lets you cut down your simulations and reduce the number of
corners you need to analyze through a "design of experiments" approach to
find problems corners and sensitivities, effectively. I didn't use this
for my evaluation with 27 corners, but it could save time if you have 100's
of corners to run.
SOLIDO MC+
PVT corner analysis isn't always sufficient. I used Solido MC+ to determine
how mismatch affected the design at different process corners. MC+ has a
lot of features and it took me a couple of days to run through most of them:
- Sweeps of the design geometries, to see the most sensitive device
devices to fix by adjusting transistor length or width.
- Runtime feedback so I could see failures on-the-fly without having
to wait for the run to complete.
- Visual analysis tools, such as selecting groups of components and
analyzing the major contributors to variation.
Speed. Before Solido, I just used Cadence's Spectre Monte Carlo. Spectre
is slow on its own; using Solido makes things a lot faster. I didn't use a
stop watch, but below is a representative example for a PLL Charge Pump.
Tool Run Time
Spectre Monte Carlo ~15 hours
Solido with Spectre ~3 hours
The difference in analysis times are from multi-threading/multi-CPU support
in Solido plus its "Optimal Sampling" approach (compared to the "Monte Carlo
sampling" method) plus its ability to explain the cause of problems without
having to run extra simulations.
In general, I saw a 5X difference between these two methods along these same
lines.
In the past only a few of our engineers ran Spectre Monte Carlo analysis on
a limited basis. With Solido, other members of my design team and I are now
running the Monte Carlo+ analyses on a regular basis.
Solido MC+ also gives you an idea of confidence in your yield estimates,
e.g. 95% +/- 5%, which goes up with further analysis. Below is what we got
for our squelch detector.
Solido simulation time Parametric yield constraint
5 hours 99% +/- 1%
Also, when we just use Spectre Monte Carlo alone to calculate our parametric
yield, we run against design extremes which means over guardbanding. With
MC+ choose a corner to a certain probability (e.g. 3 sigma), with let us
run against realistic design extremes to make sure the circuit works without
over-margining.
The foundry corners may not be worst case corners, so I use MC+ to select
them for my specific design. I use MC+ to look at mismatch and variation
associated with effects like transistor mobility, oxide thickness, threshold
voltage, to see which would break my circuit. I typically run MC+ at
SS/TT/FF corners and compare the variation versus the PVT+ corners.
Solido MC+'s "identify", "fix" and "verify" steps are similar to those I
described above for PVT+.
SOLIDO Prox+
I did not run well proximity analysis before I began using Solido Prox+,
and instead had just relied on TSMC design rules. Oddly enough TSMC design
rules state you should run SPICE analysis to determine well distances for
critical circuits. In our case, we had only considered proximity effects
when we got to layout, since we didn't know what margin was needed, so for
example we might select guard banding with 2 micron margins; but some might
require a 3.5 micron guard band.
Solido Prox+ looks at where each device is placed relative to the well. To
keep our circuit in balance, I used Solido to determine the required
distance needed to reduce well proximity effects to less than 2% of our
current mismatch specification. It determined which transistors were
sensitive and recommended what size margins to put on them. For example,
it placed certain sensitive devices in the middle of the well and others
at the edges.
Gotchas
Solido had their fair share of bugs in their earlier 2.2 product release.
The issues included not being able to print waveforms from simulation
results and not being able to save more than one state. I also noticed
that I had to run all 45 corners if only 1 corner failed to start due to
a LSF fault. (The LSR fault was not related to any Solido issue, but hey
it happens on networks all the time and re-running 45 corners could be
very time consuming.) Thankfully; however, Solido fixed all of these
issues in their 2.4 product version. Still I would like to see
Solido add an ability to report parasitic RLC or RLC values.
I have been very impressed with Solido products and continue to use them for
my analog/mixed signal SERDES designs. The applications engineers are very
knowledgeable and have been proactive identifying our needs. I would give
them an A.
- Glenn Murphy
Qualcomm San Diego, CA
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