( ESNUG 484 Item 2 ) -------------------------------------------- [03/12/10]
Subject: ( DAC 09 #1 ) Aart's nightmare -- a first look at Oasys RealTime
> #$@%&*!!! -- Aart de Geus would have a heart attack if he knew which of
> his Tier 1 customers anonymously commenting about Oasys. Sweet Jesus!
> Oasys RealTime Designer is a younger, fleet-on-his-feet, more buff boxer
> giving an elderly Synopsys a nasty kick in the company jewels (DC-Topo)
> and it's not pretty. In the 20 years I've covered Design Compiler, I've
> never seen any rival tool get such an enthusiastic initial support from
> the user base. This is the nightmare tool that would have kept Aart awake
> most nights if he hadn't diversified SNPS into other EDA spaces. Of
> course, this all depends on Oasys delivering 100% on its promise and not
> making any of the classic EDA start-up mistakes. Danger!, DC, danger!
>
> - from http://www.deepchip.com/item/dac09-01.html
From: [ The Mouse That Roared ]
Hi, John,
Please keep me and my company anonyous.
While working on a new chip we were initially struggling to get a few of our
big blocks synthesized. Synopsys DC choked due to their large size and it
was either crashing or was taking more than 2 to 3 days to synthesize.
So we decided to try 3 big blocks with 5.8M, 2.7M, 1.6M instances in Oasys
RealTime. Setup was easy. I was able to do initial setup and get it up and
running within two hours.
RealTime does not use wire load models during optimization. Instead it
partitions the design and does a congestion-aware global placement. It then
uses the placement information to calculate the approximate wire delays and
optimize your design based on this loading information.
Due to the comparitively slower runtimes and lower capacity of Synopsys DC,
we had to do "bottom up" compiles for our bigger blocks in DC. With Oasys
we didn't have to partition our big blocks in to smaller sub-blocks. We've
found this can result in a better optimized design overall as more
optimization is done closer to flat.
Our biggest 5.8M block finished in 70 min with peak memory usage under 2G.
RealTime Designer inputs:
- Verilog RTL
- .libs (CCS or NLDM)
- SDC timing constraints
- technology and library LEF files
- floorplan DEF file (optional).
In the floorplan DEF file, you can specify the floorplan constraints such as
die size, macro and I/O placement and regions to constrain physical RTL
synthesis. If the floorplan file is not specified then RealTime can come up
with floorplan by itself.
Outputs:
- gate-level netlist
- timing/area reports
- placement DEF file
The output placement DEF can be used as a seed in your downstream P&R tool.
Because of its speed, we also liked that RealTime can be used to get quick
feedback about the timing/area/power impact of our RTL design choices.
Overall I think Oasys has strong potential to replace Design Compiler.
- [ The Mouse That Roared ]
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