( ESNUG 482 Item 2 ) -------------------------------------------- [06/30/09]
From: John Weiland <john.weiland=user abraxascorp got calm>
Subject: Weiland on FastScan, TetraMAX, Spyglass DFT, Verifault-XL, TSSI
Hi, John,
Mentor has a complete line of test tools. They also have something like
20 different tools that are called "Calibre whatever" but that is apparently
not enough; I've heard some of these test tools may be renamed to become
part of the Calibre family as well, since they are related to yield.
MENT's DFT Advisor does testability analysis and inserts test hardware.
FastScan does ATPG for full-scan designs and FlexTest does it for partial-
scan or non-scan designs. Both support stuck-at, IDDQ, transition and path
delay faults. TestKompress compresses vectors by taking a single vector,
distributing it to many short scan chains and then combining results into
a single output vector. MacroTest creates scan based (non BIST) tests for
small memories and is integrated into FastScan; it's helpful when a memory
is so small that it's hard to justify the overhead of BIST. MBISTArchitect
adds Built-In-Self-Test (BIST) to embedded memories and it also supports
Built-In-Self-Repair using redundant columns and rows. LBISTArchitect
inserts BIST in logic and has a patented algorithm for test point insertion
(which is the key issue in logic BIST). BSDArchitect inserts boundary scan
around I/O. Yield Assist helps isolate failures based on failing patterns.
LogicVision, which was recently aquired by MENT, has a new release called
"Dragonfly", which integrates all their logic Built-In-Self-Test (BIST),
memory BIST, SERDES BIST and boundary scan. There had been issues in some
past releases where their paradigm seemed like a point tool with delusions
of grandeur; I'd be interested to see how much this new release impacts
your design flow. They have a new USB to JTAG interface called "Silicon
Insight" that can test a chip from a PC using a $50 off the shelf board.
They can schmoo clock frequency versus power supply, etc. The same software
can run on big testers as well.
Synopsys, Inc., sells a variety of test tools. DFT Compiler does DRCs for
testability at the RTL and gate level and can repair some gate level
problems, and inserts scan chains. TetraMAX generates ATPG for stuck-at
faults. The TetraMAX IddQTest option (enough with the weird capitalization
already!) creates vectors for IDDQ testing. The TetraMAX DSMTest option
generates vectors for transition faults and path faults as well. The T-MAX
TenX option allows it to run on multiple processors (up to 10 of them).
Boundary Compiler can synthesize and optimize boundary scan, check it for
compliance with 1149.1, and generate boundary scan vectors. DFT Max
compresses vectors (they claim by 10X to 100X) by scanning in a single
vector, distributing it to many short chains using "adaptive scan", and
combining the results.
DAFCA sells IP and SW for debug that basically creates a logic analyzer
on-chip and allows transaction level analysis and checking of assertions.
They claim that they reduce the time from first silicon to final silicon
by about 30%. The user can trigger the software with the hardware being
debugged and vice versa. This tool is not cheap but if it gets you to
market a few months earlier it could be well worth it.
Atrenta sells Spyglass DFT, which does Design For Test analysis of RTL code.
They claim it has a very high correlation (1-2%) with final fault coverage
numbers. It supports stuck-at and at-speed testing, and has an Auto Fix
feature to tweak your RTL for better testability, which they say is much
easier than trying to tweak your netlist.
Most of the really fast fault simulators do not use actual delays. That is
fine if you have well behaved logic but sometimes you get designs (legacy
blocks, etc.) which sadly will only work with timing. There are not many
choices here. Cadence Verifault-XL is one but it's had no real development
since NC-Sim came out a decade ago and they never created an NC-Fault
because the market is pretty small.
Syntest sells a Verilog fault simulator that takes SDF that is much, much,
much faster than Verifault-XL. On some test cases I've seen it hundreds of
times faster (hard to believe). It's faster because of a number of tricks.
One trick is that they provide a script to remodel the library to use their
own primitives rather than UDPs. Sometimes the script handles the whole
library as-is in a few seconds, sometimes you need to play with a few of
the cells which requires that you understand Verilog cell modeling. They
also sell a complete line of test tools, including tools for scan insertion
and ATPG, memory and logic Built-In-Self-Test (BIST), and test compression.
In general, they seem much more technically oriented in their presentations
and much less glossy, which may be why they have issues selling outside of
Japan. They said that new for this year, they will be switching to one-hot
clocking for initial ATPG and then go to staggered capture only for faults
between clock domains (case in point).
Winterlogic also sells a Verilog fault simulator that can use SDF. They
said you do not need to remodel the library (as with the Syntest tool).
After running the vector files on the "good" machine only, they say they can
rank the tests for fault coverage so you know which simulations to do first
(pretty good trick -- I wonder how well they do that).
Genesys Testware sells tools for memory and logic Built-In-Self-Test. In
addition to Built-In-Self-Test (including memory retention testing) and
Built-In-Self-Repair of soft errors (no fuses needed), they also support
embedded boundary scan. They can also create boundary scan around
individual blocks to that testing can be done hierarchically, and they can
support testing of interconnect between chips. New for this year is support
for testing power shutoff switches. They support Synopsys, Cadence and
Magma. Insertion is during synthesis; there are no RTL changes. Input can
be RTL or gates, output is always gates.
Virage Logic has STAR (Self Test And Repair) for their memory compilers.
TSSI (Test Systems Strategy, Inc.) is the largest provider of software to
translate and process tests from generic formats (like STIL or WGL) into
the formats needed for specific testers. They have been working to improve
their software to simulate a tester, so that you can debug your test
program without tying up a $5M tester. They can now simulate mixed signal
tests and have a C/C++ backplane for mixed signal simulation.
National Instrument sells software and hardware to turn a PC into a basic
tester. Capabilities are obviously more limited that a production tester
and cost is a tiny fraction of what production testers cost.
The Design Technology Center at National Tsing Hua University in Taiwan had
a booth at DAC last year presenting a couple of research projects. If I
understood the explanation correctly, one project was a scheme for testing
parts without probing I/O. You would power up the chip and use a wireless
on-chip transceiver for functional testing. Obviously there are lots of
issues like packaging extra parts that will fail parametric testing, but for
high pin count, low volume parts the economics of this approach might work.
- John Weiland
Abraxas Corp. Columbia, MD
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