( ESNUG 481 Item 5 ) -------------------------------------------- [05/08/09]
From: John Weiland <john.weiland=user abraxascorp got calm>
Subject: Weiland on Mentor Veloce, Synplicity HASP, Dini, EVE, Aldec, Gidel
Hi, John,
Be very careful about gate-count claims here. There is a huge difference
between raw FPGA gates and equivalent ASIC gates (close to 10 to 1) so be
careful when comparing different vendors boards and boxes.
Mentor sells their Veloce and VStation Pro lines of big box emulators. They
say they can emulate up to 128 M ASIC gates, compile about 15 M gates/hour,
simulate at up to 1.5 MHz, support SVA, PSL, OVL and 0-In CheckerWare
assertions, and claim 100% visibility without recompiling.
Mentor also sells a tool called Testbench Xpress that allows you to use a
transaction level testbench to communicate with the emulator (so the
emulator spends less time waiting for the computer to catch up). They also
allow you to add various processors (such as ARM7, ARM9 and ARM11) to the
accelerator using "iSolve".
Synopsys bought Synplicity, which had previously bought Hardi, so they have
the HASP (High-performance ASIC Prototyping System) family of boards. They
say their largest boards have up to 4 Virtex-5 FPGAs which can emulate
8 million ASIC gates, can operate at "100s of MHz" (??), and can be easily
ganged together with each other and with daughter cards with Ethernet, UDB,
PCI, ARM and other functions.
Synplicity also sells Certify, which partitions an ASIC prototype onto
multiple FPGAs and does automatic multiplexing of pins, insertion of probes,
and handling of ASIC-specific structures like clock trees.
The Dini Group emulator boards are now based on both Virtex-5 and Stratix-3
FPGAs. They can fit up to 16 Virtex-5 parts on a board for about 32 million
gates, and their board with 6 Stratix-3 parts can fit up to 15 million gates
and run up to 1.2 Gbps between chips (obviously depending on your circuit).
Gidel sells boards that are can be ganged together and they say can handle
up to 180 million ASIC gates. Their top of the line boards use Stratix III
340s, which are currently the highest performance FPGAs. Boards can operate
up to 350 MHZ depending on the circuit.
Aldec supports prototyping boards. They say they a partnering with
Synopsys/Synplicity/Hardi and the Dini Group so I’m not sure if they
actually produce anything. They do sell software to partition an ASIC
into multiple FPGAs for prototyping. It is targeted at emulators (with
multiplexers at the I/O) and works on a flat netlist.
EVE sells a range of both emulators and probably the only true hardware
accelerators still being sold. The hardware accelerators can go up to 500
million gates, while the emulators top out at around 100 million. They
sell versions for hardware-software co-development, I’m assuming with
reduced debug capability. They have a new "Zebu personal" board with two
Virtex-5s that will hold about 5 million gates.
Dynalith sells a variety of emulator boards and associated software. Their
FPGA boards contain up to 20 million gates, they have boards with ARM 11 and
ARM 9 processors, and they also have small "educational" boards.
A German company called ProDesign sells moderate sized emulator/prototyping
boards called CHIPit. I believe they sell less expensive boards with no
debug capability, for use by software developers after the hardware folks
have a working netlist. New for this year is a tool for partitioning and
synthesizing your design (synthesis uses Precision). Synopsys recently
aquired either part or all of ProDesign; I'm not sure which.
Liga Systems sells an accelerator for RTL (their specialty) or gate level
simulation. It is a VLIW processor aimed at RTL simulation. It happens to
be implemented on an FPGA, but this is not an emulator. They can compile
the RTL equivalent to about 10M gates in an hour, and the board holds the
equivalent of up to 300M gates. They co-simulate with Mentor or Cadence
and they claim 10X to 100X speedup because they accelerate the whole
language (even the testbench), not just the synthesizable portion. Gate
level simulation is without timing. They currently are Verilog only with
VHDL coming. They currently support OVL assertions with SVA coming.
Interestingly they say they are seeing 10X more interest in System Verilog
than OVL.
- John Weiland
Abraxas Corp. Columbia, MD
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