( ESNUG 479 Item 7 ) -------------------------------------------- [02/05/09]
Subject: ( ESNUG 478 #1 ) Synopsys ICC, Magma Talus, Sierra, Atoptech
> Since Gary Smith warned (in Oct when Fister resigned) that Cadence might
> discontinue its IC CAD division, my boss wants me to find the current
> viable PD replacements for SoC Encounter. Our next chip is TSMC 45GS.
From: Jeff Echtenkamp <echtenka=user domain=broadcom hot mom>
Hi, John,
If you are looking for a Cadence replacement, you only have four choices:
Synopsys ICC, Magma Talus, Mentor Sierra, or Atoptech Aprisa
All four have gate-to-GDSII (including SI, CTS, OCV, etc), and all four have
tapeouts and have been used in production.
- Sierra and Atoptech can use LEF/LIB.
- Synopsys requires Milkyway (not sure about a path from LEF/LIB).
- Magma requires Volcano (which can be made from LEF/LIB).
They all offer some support of MCMM, but their implementations vary as does
success.
Pyxis and JSpeed (to my understanding) are just router tools, so they are
not full replacements, you'll have exposure to Cadence still.
Tuscany and Azuro, again are just point tools, so you would still have
exposure to Cadence and miss your manager's goals.
- Jeff Echtenkamp
Broadcom Corporation Irvine, CA
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Little ]
Hi John,
Please keep me anonymous on this.
Recently, I had helped a company do a thorough evaluation of the P&R tools
from all the major vendors. We evaled Synopsys ICC, Cadence SOC Encounter
and Magma Talus.
We had given two designs (both in TSMC 65G):
- a small one without any macros, and
- another slightly large one with a lot of complexity like datapath,
complex clocking etc.
Our results actually put all three fairly close in both evaluations.
- As expected, we found some weakness in Magma router, but their R&D
had suggested fixes very quickly.
- We also found that Synopsys Z router has matured fast and is in
fact highly competitive against Nanoroute.
- Cadence SoC Encounter still had some nifty features like RDL routing.
Finally, we selected Synopsys ICC based on what suited to our designs the
best, as well as other considerations.
> Synopsys IC Compiler: reputation good but you must be an expert to use.
> Set 1 of 1001 switches wrong and runtime is a week or never converges.
> They're merging J-XT into ICC, so its floorplanning is more complex.
> Global vs. detailed routing? SI? OCV? CTS? ICC weak in MCMM. We will
> need SNPS consulting to run ICC. Will this hold us back? Libs available.
> Will this lock us into a Synopsys-only flow? Boss fears dependence on
> one vendor for all tools.
Contrary to what this engineer thinks, ICC worked out of the box with very
few settings needed. For our next design we are pondering TSMC 45GS.
My earnest advice to your ESNUG readers is that every design is different
and you need to evaluate these tools on your designs to make a meaningful
decision.
The considerations should go beyond just the design support -- like tool
cost and support, because this can make more sense than the tool itself
nowadays.
I think designers can benefit a lot (save real $$) by employing an expert
who is impartial to these vendors to conduct an evaluation if they have
time (about 3 months). It doesn't take a lot of engineers to do these
evaluations.
- [ Chicken Little ]
---- ---- ---- ---- ---- ---- ----
From: [ Soylent Green ]
Hi, John,
The economy has soured significantly since DAC. Because it's a relatively
small start-up, is Atoptech still a viable business option to replace SoCE?
- [ Soylent Green ]
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