( ESNUG 479 Item 3 ) -------------------------------------------- [02/05/09]
From: [ Papa Smurf ]
Subject: Magma Mojave Quartz did 1.5 B Transistor sign-off DRC in 4 hours
Hello John,
We just taped out a 1.5 B transistor processor in 45 nm SOI and we have a
real sense of accomplishment from it. A big part of this is being able to
DRC such a chip, and Magma's Quartz DRC really came through for us. It is
our sign-off DRC tool.
We started using Quartz early 2006. We initially qualified Quartz in
parallel with our 65 nm production DRC tool using Quartz DRC as a back-up.
For 45nm Quartz is our production tool. We selected it because of:
1. Performance, both current and expected for future - given anticipated
growth in chip size, DRC rule quantity and DRC rule complexity. Its
distributed processing was important here, I have more on this below.
2. Flexibility, the tool's ability to adapt to new rules which did not
already not exist or were not implementable with current DRC tools.
We were also looking for timeliness and accuracy for production of
new checks in leading edge technologies such as 45 nm and below.
3. Deck development complexity. How difficult is it to maintain a DRC
deck. We own our DRC decks so this is important to us.
4. Accuracy. Somewhat of a given so this is last. Accuracy for DRC is
largely yes or no, right answer or not -- we do not have any problems
with Quartz' accuracy. For some unique rules the issue is "ability to
do the check at all".
Quartz DRC's distributed processing was a major selling point for us, since
we need to get multiple turns of full chip DRC in a day to get good design
quality and to meet schedule.
We did initial scalibity studies 3 years ago from 1 to 100 processors and
found it was roughly linear up to 100 processors. We were surprized and
impressed with that. But that was 3 years ago with a 65 nm design that had
much simpler DRC rules.
Now at 45 nm to get 4 hours we needed 16 CPU's. This is a much larger chip
with messier DRC's. We were quite happy with the 4 hours. Next on my To Do
list is to see if we can get it down to 2 hours using between 16 and 32
processors in 2Q09.
Another plus is that Quartz is TcL based runset. How can we not love having
an industry standard interpretive language as the DRC language?
Quartz DRC weaknesses:
1. It took about 3 years for a buggy Quartz to move from a "good idea with
potential" to what is now a feature rich tool.
2. The next problem was processor scalability of full chip connectivity
checks. It needed to get under 4 hours for full chip DRC, which it is.
3. Our next headaches are production quality incremental and pattern
matching DRC's in Quartz.
Because we do both custom and cell-based PNR. We have a fair number of checks
other than base DRC:
- yield or DFM checks to enhance product quality
- methodology checks to guide the methodology.
That is, DRC is much more involved for us vs. a standard ASIC design.
Mojave applies yield rules throughout the chip, yield being both defect
limited yield and performance (or circuit) limited yield. For example,
modeling via coverage and reporting the percentage of times it passes the
rule, or the CA, RX and PC corner rounding for device modeling.
For methodology, Mojave does power pin and signal/clock pin checks, power
via distribution, relationships presumed (but possibly not checked) by LVS
such as fill cell connectivity and boundary condition checks.
We're very happy with our functional results using Quartz. We have working
45 nm chips in the lab now. We expect our movement to 32 nm will be largely
an extension of what exists in 45 nm.
- [ Papa Smurf ]
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