( ESNUG 478 Item 1 ) -------------------------------------------- [12/18/08]
From: [ Sideshow Bob ]
Subject: With Gary Smith's warning, what should replace SoC Encounter?
Hi, John,
Since Gary Smith warned (in October when Fister resigned) that Cadence might
discontinue its IC CAD division, my boss wants me to find the current viable
PD replacements for SoC Encounter. Next chip is TSMC 45GS. What I know:
- Synopsys IC Compiler: reputation good but you must be an expert to use.
Set 1 of 1001 switches wrong and runtime is a week or never converges.
They're merging J-XT into ICC, so its floorplanning is more complex.
Global vs. detailed routing? SI? OCV? CTS? ICC weak in MCMM. We
will need SNPS consulting to run ICC. Will this hold us back? Libs
available. Will this lock us into a Synopsys-only flow? Boss fears
dependence on one vendor for all tools.
- Magma Talus: replaces buggy ver of Blast. New Hydra floorplanning.
LAVA tools much better ease-of-use. Can they do MCMM? SI? CTS? OCV?
TSMC libs avail. Has anyone tapeout with a full Calibre DRC signoff?
If MENT acquires LAVA, which PD toolset will MENT kill off?
- Mentor Sierra: architected for MCMM. How difficult to use? Are there
libs? Any production tapeouts yet? SI? CTS? Global/Detailed routing
quality? OCV? Etc. Has anyone done a complete chip in a Sierra-only
flow yet? If MENT acquires LAVA, which PD toolset will MENT kill off?
- AtopTech: same Q's as Sierra.
- Pyxis: same Q's as Sierra but stronger in DFM. Don't know if MCMM.
- Jspeed DA: same Q's as Sierra. Don't know if MCMM.
- Tuscany and Azuro: PD optimation add-ons to our existing CDNS flow.
Should we take this path instead of doing a full PD swap out? Do
they use CDNS libs? What about MCMM? Any known full DRC tapeouts?
My group doesn't have the time nor resources to do an 8-way PD benchmark.
Plus we don't want to be harassed by all those EDA salesmen.
Which flow should I recommend to my boss that we benchmark?
- [ Sideshow Bob ]
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