( ESNUG 476 Item 10 ) ------------------------------------------- [10/29/08]
From: [ Tennessee Tuxedo ]
Subject: Packing guy asks on going from wirebond to flip chip and EDA tools
Hi, John,
I ran into ESNUG on the web and it's obvious your readers know their way
around all design tools, so I am hoping they could help me out.
I am a packaging guy that used to work at an IBM fab location; so I know a
bit about chip design, but it's dated.
Basically I am trying to figure out the following:
1) When people design for flip chip today do they design with the I/O
placed anywhere on the chip & put flip chip balls near there, or are
they doing the old-fashioned way of putting all the I/O around the
chip periphery and then routing with metal to the ball locations?
2) Question 1 is related to the design tools available I guess - so if
they are placing I/O anywhere on the chip this must mean design tools
are available. If that is the case - what % of companies have those
design tools with that level of flexibility?
3) If you are working with old design tools and needed to transition to
flexible flip chip design tools - what would it cost and how long
would it take? If you had one chip design that was originally
designed for wirebond, but then had another metal layer added to
re-route the peripheral bond pads to area array flip chip ball
locations - and you wanted to move this design to an optimized design
for flip chip (design with I/Os placed optimally) - what is the cost,
time, effort required?
Appreciate any input your readers might have. I have to be anon on this.
- [ Tennessee Tuxedo ]
Index
|
|
