( ESNUG 476 Item 8 ) -------------------------------------------- [10/29/08]
Subject: ( ESNUG 470 #1 ) Mentor TestKompress and EDT kicks ass in China
> Owning DEF means they can use DFT MAX or TestKompress easily. From a PD
> view, Mentor owns TestKompress but Sierra is still a raw tool, hence
> they're #3. Magma has no compression and I don't know if they can even
> support DFT MAX nor TestKompress. Atoptech a newbie here.
>
> - Jonathan Bahl
> COT Consulting, Inc. Toronto, Canada
From: [ Singapore Slim ]
Hi, John,
Please keep me as anonymous.
We successfully used Mentor EDT (Embedded Deterministic Test) in a complex
SOC design. Multiple EDTs were used. Mentor EDT helped reduce the top
level IO pin multiplexing and shortened our test time without sacrificing
test coverage. EDT was easy to integrate into SOC design.
I also received excellent support from the Mentor Singapore AE.
- [ Singapore Slim ]
---- ---- ---- ---- ---- ---- ----
From: Hao Fang <fanghao=user domain=mprc.pku.edu.cn>
Hi, John,
We are implementing TestKompress on a 7 million instance project. It's a
modular design and both stuck-at and at-speed patterns are considered.
Our coverage for SAF is 98%+ and TDF is 85%+.
We're also using MBISTarchitect for memory BIST generation on ~100 memories.
Generally speaking, the complete Mentor DFT flow with good quality patterns
is critical to us. I am glad that Mentor DFT can help on us.
- Hao Fang
Peking University Beijing, China
---- ---- ---- ---- ---- ---- ----
From: Zhou Lei <lei.zhou=user domain=freescale not calm>
Hello John,
We taped out a design which contains 49K FFs. It's a dual-core programmable
CMOS digital signal processor (DSP).
We used Mentor DFT tools to reduce test cost significantly.
The first technique was adding EDT logic to compress our pattern data. And
the logic occupied less than 1% area of the chip. With compression, our DC
scan pattern volume is only 3.21 M compared to 61 M without EDT. (A
compression ratio of about 19.)
The same story happens in AC scan. The pattern was volume is 8.25 M compared
with 185.91 M without EDT. The compression ratio was about 22.
By combining the stuck-at and transition test patterns with the on-chip
compression logic, the amount of required tester memory drops to just 5% of
the memory that would be required without the on-chip compression logic!
That reduces our test cost significantly.
Another big test cost saving was that we used a small area logic to produce
at-speed test purpose. Since we were able to produce a high frequency clock
in capture state, we can use a less expensive tester while still testing the
design at its 200 MHz operational frequency. Considering that a 1000 MHz
Pinscale tester is almost double the cost of a 100MHz J750 tester, the test
cost is cut in half by using this technique.
- Zhou Lei
Freescale Semiconductor Shanghai, China
---- ---- ---- ---- ---- ---- ----
From: Ben Liu <ben.liu=user domain=amd not calm>
Hi John,
TestKompress worked quite well on my 7.5M gate design, which was taped out
already. I couldn't imagine how we finish jobs without modular EDT since
we have 4 independent cores in my design. The final compression rate was
63X; quite impressive. Saved us lots of manufacturing cost indeed.
I am also pleased no coverage loss (97.5%) even under such compression rate
since quality is critical to us.
- Ben Liu
AMD China
---- ---- ---- ---- ---- ---- ----
From: Ming Ji <mingji=user domain=trident.com.cn>
Hi John,
I have used TestKompress for years. By using it with TetraMax (which I
used before) TestKompress was able to reduce 50% DPM with its new fault
model detecting schemes with even much lower test cost (down to 10% only).
Besides this, Mentor always delivers good technical support, too.
- Ming Ji
Trident Shanghai, China
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