( ESNUG 476 Item 1 ) -------------------------------------------- [10/29/08]
Subject: ( ESNUG 475 #5 ) Boatload of users talk up Mentor Sierra MCMM P&R
> The only blindingly obvious hole was Mentor's; only one user commented on
> Calibre and not one person noticed Mentor's Olympus-SoC nor Pinnacle tools
> which they had bought from Sierra for $90 million last year. Not one!
> What if you held a party and nobody came? Ouch...
From: Nanda Lekkelapudi <nanda=user domain=mips not calm>
Hi John
I saw your comments on DAC (ESNUG 475 #5), got a nice chuckle but here's my
opinion on Olympus.
I attended the Olympus demo in Mentor pavilion at DAC this year. I found
the tool to have all the bells and whistles that you find in comparable P&R
tools. The demo focussed on some of the low power design aspects. They
talked about their MCMM methodology and low power features such as voltage
islands (Multiple VDD) combined and power state analysis. Impressive. The
demo also talked about power optimization in CTS across multiple corners.
Overall they demonstrated a compelling solution. We use the 3 major P&R
tools (ICC, SOCEnc, Talus) here, but personally I have used only Talus and
SOCEncounter. I would definitely consider Sierra if I had to do a fresh
P&R tool evaluation.
- Nanda Lekkelapudi
MIPS Technologies, Inc. Mountain View, CA
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From: [ The Invisible Man ]
Hi, John,
In response to your recent ESNUG DAC report, we just taped out with Olympus.
Our design was a macro embedded in a chip used for serial interface with a
750 Mhz clock.
We had a design issue related to high design density. There were 4 modes,
including a low power mode and 4 corners per mode, and we had to ensure that
the clock tree considered all these different modes and corners.
We specified the constraints up front in the design cycle for all the 16
scenarios (4 modes, 4 corners). All of their engines honored all of the
MCMM specifications. We completed the implementation without any hiccups.
We were also pleasantly surprised with the flexibility of Olympus-SOC's
CTS engine and also the ability to perform MC optimization during CTS.
When we started using Olympus, some features were still immature but we
could see the improvement from release to release. Sierra's R&D is really
reactive and as we have a good relationship with them that helps us resolve
problems faster. Overall we have been happy with the Olympus tool.
We went from netlist to GDSII in the Olympus system. It worked.
- [ The Invisible Man ]
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From: [ The Horse With No Name ]
Hi, John,
Please keep me ANON.
I did attend DAC, but did not spend much time at the Mentor booth as we are
currently use them (since being Sierra) for our P&R flow and have seen all
of their presentations.
We currently use Pinnacle in our design flow and are quite impressed with
it's capability to close top level timing, either in global, full flat, or
mixed mode timing. (Its implementation technique has been precise enough
to close global timing with very small perturbation of our underlying
hierarchies.) Pinnacle's capability to close very large designs in MCMM
mode, with reasonable turn times and good results appears unique. I haven't
found that with Synopsys/Magma/Cadence you could do this.
Sierra R&D has been very responsive to fix issues, as well as enhancements.
Currently we use Magma for block-level design and Sierra as our top-level
tool. I'm looking forward to evaling Olympus on all levels next.
- [ The Horse With No Name ]
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From: [ The Cheshire Cat ]
Hi, John,
I saw your comments in the recent ESNUG DAC report about "Where was Mentor
Sierra?". I went to their Low Power P&R demo and thought it was one of
the better demos at the show.
There were 2 things that caught my attention. First, they didn't just make
the inevitable claims about being X% better than anyone else. They gave
explanations about *why* they could achieve better results. This was mostly
due to their timing data model (multiple virtual timing graph technology;
supposedly patented) and highly scalable algorithms.
This allowed Pinnacle to optimize for multiple mode/corner multi-power state
scenarios concurrently while honoring the various power domain requirements
throughout your flow. One area that looked particularly interesting was
some of the clock tree optimizations they are doing. (Power modes are
effectively timing modes so being able to handle multi-mode timing is a key
building block for power modes.)
The second thing about the Sierra demo was in some of the details. Multi-
mode was clearly well thought out not just in what is under the hood but
also the presentation to the user. The timing reports for example showed
how timing and power varied across each scenario in a single report. It
might not sound like much but being able to see the effect of an incremental
analysis or optimization run across all modes and corners automatically
in a single report sure beats having to crawl through a dozen or more
separate reports to see what is going one. They had clearly thought about
the use model.
- [ The Cheshire Cat ]
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From [ The Man In The Iron Mask ]
Hi, John,
Please keep me anonymous.
Our last design was done in TSMC 65 nm. We outsourced our place and route,
but had difficulty in closing timing and DRC. We plan to do our next design
which will be high speed in TSMC 40, so we'll need to bring P&R in house.
So at DAC we looked at Synopsys, Mentor and Magma.
The Mentor (Sierra) Olympus-SoC low power demo that I saw at this year's
DAC still remains in my mind for two reasons:
1. I wanted to see the Olympus-SOC concurrent multi-corner multi-mode
analysis in action. I have been involved with many low power designs
and this has been my passion for the last several years now. Tools
are increasingly supporting low power features. For example, Dynamic
Voltage and Frequency Scaling (DVFS) is getting a lot of attention
lately, and this technique requires supporting multi-corner multi-mode
very efficiently. This includes optimizing across multiple corners
as well as clock tree synthesis for multiple corners.
2. The size of the design that the Mentor demo was built on was an 80K
instance block. It had very fast optimization runtimes.
- Mentor claimed Olympus-SOC could read a 100M gate database
in just 15 minutes
- Mentor claimed that a complete placement with optimization on
the 80K design was not more than 3 hours.
The presenter stated that an Olympus-SOC timing update including
crosstalk for a 10M gate design was less than 1 hour/corner.
One of the requirements for our design is to do timing updates very fast.
In my mind, Olympus has the best capacity and runtime for MCMM today. In
particular, we are very interested in incremental timing updates. Sierra
looks promising because it only builds a timing graph once then updates the
timing graph during optimization. This is in contrast to the more common
approach of rebuilding the timing graph after each optimization iteration
which is very time consuming for a full chip analysis.
- [ The Man In The Iron Mask ]
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From: [ The Phantom Of The Opera ]
Hi, John,
I saw two Mentor demos at DAC: Olympus low power P&R and Olympus-Calibre
integration. Both the demo's were very interesting, particularly the
Olympus-Calibre integration. We use Synopsys and Magma for placement
optimization, CTS and routing. Pinnacle is used for MCMM optimization.
We use Calibre as our physical verification and signoff tool. Our current
solution for fixing Calibre reported DRC/LVS violations is a semi-automatic
flow. It is iterative and time consuming. Since DRC/LVS fixing is gating
element for tapeout, any flow improvement in this area is very useful.
Olympus integration with Calibre allows us to have a more automated flow
for signoff DRC/LVS fixing.
The demo showed how Olympus fixes Calibre reported DRC/LVS violations and
incrementally runs Calibre on the modified design.
We would like to evaluate this Sierra flow to see if it adds value.
- [ The Phantom Of The Opera ]
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From: [ Batman ]
Hi, John,
Please keep this as an anonymous posting.
I read your recent post of DAC on ESNUG and here is my take on the Sierra-
Mentor integration. I attended the Olympus-SoC demo and basically Mentor is
focused on DSM design, with emphasis on design capacity, low power design
and overall timing closure.
Of special interest to me was their capability to do true MCMM analysis
(even during CTS) and optimization and the ability to route large designs
in a litho-friendly fashion. Aspects of adaptive variability were also
highlighted. Using UPF is a plus, too.
They seem to be a unique player claiming they can do low power, variability
aware, time-to-market all at once.
- [ Batman ]
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From: [ The Green Lantern ]
Hi, John,
I gotta be anon here.
I attended the Olympus-SoC demo and it looks like Mentor now is on the low
power design bandwagon as well. Their demo talked about 45 nm design
challenges like routing rules, capacity, variations and mostly low power.
Just like the other vendors they started talking about the challenges of low
power and got into discussions about MVDD flow etc. What caught my interest
was their spin on leakage aware and MCMM aware low power design. Sierra's
claim to fame is their MCMM opto and they seem to be leveraging that angle
to solve the low power puzzle.
Apart from the generic techniques the Sierra demo highlighted the MCMM role
in DVFS designs and also MCMM based CTS which I thought were unique. Based
on what I saw I felt that Sierra is building on the MCMM architecture and
playing to its strength.
- [ The Green Lantern ]
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From: [ Hello Kitty ]
Hello, John,
Please keep my name as anonymous.
We use Pinnacle in post-CTS MCMM fix and post-route fix (with SDF files from
signoff RC extraction) in most of our projects.
We had a problem using SDF with incremental SDF (created by our noise check
tool) in their post-route fix flow. Mentor patched this problem in release
2008.04.P5. So far we are happy with their service and their results.
- [ Hello Kitty ]
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From: [ Captain Obvious ]
Hey, John,
I have been following the progress of Sierra at DAC for the last 3 years,
but it wasn't until the acquisition by Mentor that my company was able to
even take a look at Olympus in any formal way. (Since then we now access
Olympus under our existing Mentor contract.)
My team and I did not spend much time at the Mentor booth at DAC since
we can get all of that information at any time just by picking up the
phone. We go to DAC to look at tools that we don't currently have
access to, so that we can see what we might be missing.
I would prefer if you would keep my name and company confidential.
- [ Captain Obvious ]
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