( ESNUG 475 Item 1 ) -------------------------------------------- [09/18/08]
Subject: Forte Cynthesizer, Mentor CatapultC, Target, Imperas
GARY'S HAPPY (PART I): Gary Smith has predicted for years that SystemC based
design was going to take over the world. We'll at least users are noticing
them now. While Mentor marketing likes to give the impression that their
CatapultC dominates the C design business; from what I'm seeing is it's more
of a 50/50 thing between them and Forte.
"What were the 1 or 2 or 3 INTERESTING specific tools that you
saw at DAC this year? WHY where they interesting to you?
(If any were under NDA say it and I'll keep you anon on them.)"
---- ---- ---- ---- ---- ---- ----
Forte's Cynthesizer, because its space seems to be more general and it
uses SystemC as input (instead of C++ plus proprietary constraints).
- [ An Anon Engineer ]
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Forte's Cynthesizer:
ESL was a hot topic at this year's DAC and with a number of approaches
shown including clean-sheet languages, plain old C-to-gates, and Forte's
SystemC synthesis. Clean sheet approaches are academically interesting
but aprobably headed for a sociological brick wall. Vanilla C-to-gates
tools just ignore physical reality and take an orders-of-magnitude QoR
hit, or result in a frustrating bait-and-switch where unsuspecting users
end up recoding to a poorly defined semantic that is nothing like what a
C programmer grew up with.
Forte's approach builds on SystemC in a manner that is reminiscent of
HDL synthesis in its infancy, where a synthesizable language subset was
introduced into a framework originally designed for simulation. Their
environment offers a clear semantic for concurrency, communication and
structure, and building on C++ enables codesign of the SW components of
a system. Longer term, users targeting programmable platforms may also
find that this Forte approach gives better scalability and mobility
between FPGAs and emerging stream computing platforms based on arrays
of light-weight processors.
- [ An Anon Engineer ]
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We expect Forte's Cynthesizer to rescue our RTL developers from the
endless perfectionism of our DSP architects.
- Yong Miao of Fujitsu
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I attended the Forte Cynthesizer demo and found it very interesting.
I think it could potentially automate one part of our design process
which is currently cumbersome and error prone.
As far as the demo goes, perhaps attending a workshop where I could try
the tool firsthand would have given a better feel for the product.
- Srikanth Shubhakoti of Marvell Semi
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We are interested in synthesizing RTL for our SoCs that process network
protocols and traffic. We are considering Forte Cynthesizer as one of
our qualified tools because one of our colleagues in another project
introduced it to us. That's why we are interested in Cynthesizer.
- Ikuo Harada of Nippon Telegraph and Telephone Corp.
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The reason why I visited Mentor's booth to see CatapultC demo was that
it had been said to be the best (and most popular) tool for synthesizing
HW from C/C++.
I saw less progress than I had expected in C-based design tools (or ESL
design as a whole). Forte's Cynthesizer was still there and NEC was
promoting CyberWorkbench, but they didn't look booming.
But my impression after seeing the demo of CatapultC is that they are
improving continuously and synthesis from C is now practical. Especially
the interface synthesis support of CatapultC seems to allow the designer
to focus on just the behavior or algorithm in C. More importantly, I was
told that they had newly started a university program, which I was most
interested in.
- [ An Anon Engineer ]
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CatapultC is a very promising tool since it shows that after many years
of research, C-based synthesis has reached a mature level in industry.
But it also shows that a good understanding of the intended hardware as
well as good C code are mandatory to achieve good results. CatapultC is
powerful because it enables the designer to transform C-coded algorithms
to hardware and evaluate different implementations in terms of their
performance and resource requirements very quickly.
- Wolfgang Rosenstiel of the University of Tubingen
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CatapultC from Mentor. I think it has the potential to help designers
to tackle larger and more complex designs. Unfortunately this tool is
still in a pretty early stage of development. I was told that CatapultC
can only handle mainly algorithmic designs for now. I'm working in the
area of packet switching networks and so can't find much use from it yet.
But I'm really interested in seeing its future development.
- [ An Anon Engineer ]
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Mentor's CatapultC allows you to describe your design in C/C++. The tool
will then convert your generic C code into RTL code, at which point you
can take it through Design Compiler to gates. It can be go to RTL for IC
implementation, or to go to FPGA devices for prototyping, or both.
I like to use generic C/C++ code for system design because it lets me
describle abstract design intent without worrying too much about detailed
hardware microarchitecture. We do lots of digital signal processing and
prefer to simulate in C++ using CatapultC's algorithmic C (ac) integer and
fixed-point data types during the algorithm development because they run
faster. We don't use SystemC integer and fixed-point data types as often
because they have too much overhead and run slower. But if you want, "ac"
data types do provide conversion methods that allow you mix and match "ac"
and "sc" data types in the same design.
At DAC, Mentor showed how CatapultC could be used for a design style based
on the idea of parameterized object oriented design. This was a very
interesting concept and matches our way of thinking. We are trying to
parameterize our algorithmic IPs described in C/C++ and split out
different designs for different requirements.
- [ An Anon Engineer ]
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Target ASIP: their tool makes the very difficult tasks of creating
multi-core SOCs practical
PDTi SpectaReg: first register development automation tool that
really works as a web application
Mentor CatapultC: well thought out strategy, integrates well with
overall Mentor flow
- [ An Anon Engineer ]
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1.) I thought the Open Virtual Platform (OVP) tools by Imperas are
really impressive. The tools help you build simulators for processor-
based platforms, and they have support has many of the important
processor models used in current designs: ARM, Tensilica, MIPS, and
SPARC. The tools come with a library of common peripherals, and
defines an interface for building custom peripherals.
It's really easy to piece together different designs. I'm working on
1000+ core processor simulations, and I was able to get a 1024 core
system running the Dhrystone benchmark at 454 MIPS in one day. That's
an incredible turn-around time for such a large system, and it's
fantastic performance for this detailed a simulation tool. Best of
all, I can use normal development tools like gcc and gdb to observe
what is going on inside any of the cores.
OVP could be an extremely useful tool for both research and embedded
system development. Since it is open-source, this could also end up
being the next SimpleScalar for computer architecture research.
- Andrew Putnam of the University of Washington
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