( ESNUG 473 Item 12 ) ------------------------------------------- [05/29/08]
Subject: Viewer's reactions to Wally's Ending Endless Verification video
> In his keynote address, Wally Rhines talks about scan, ATPG, BIST,
> test pattern ordering, cost of test, Janusz Rajski, don't cares,
> coverage, at speed, stuck at, compression, transition and bridging
> faults, cycles-per-test vs. tests-per-cycle, 70% of design is test,
> design reuse, power, multiple clocks, server farms, GRID, brute
> force, FPGA prototyping, emulation, assertions, late designs, RTL
> simulators, intelligent test benches, constrained random, dynamic
> formal, TLM, abstractions and his Q&A follow-up.
>
> See http://www.deepchip.com/videos/wally08.fhtml
>
> After viewing his keynote, feel free to send your reactions. - John
>
> P.S. No registration, no sign up, my videos are now for all to see!
From: Sankara Narayanan <sanarayanan=user domain=nvidia not calm>
Hi, John,
That was a brilliant presentation. Thanks a lot for making it available
on the web.
- Sankara Narayanan
Mvidia
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From: Dave Chapman <dave=user domain=goldmountain not calm>
Hi, John,
Well, I watched Wally's talk and I guess it was OK.
My gut reaction is that, while Mentor and the rest of them may be willing
to talk about how important verification is, the companies who are paying
to have chips designed still think of verification as an optional thing
that they'd really like to cut back on, or preferably get rid of.
There are social and cultural reasons for this.
Most of the relevant managers and executives who used to be chip designers
come from a time when there was no such person as a "Verification Engineer",
and they simply don't respect people who take a job in that role.
During the 2001-2004 recession, the verification people were the first to
get laid off, and I figure the same thing is going to happen again, soon.
So, my gut reaction is that the companies still don't really want to have
verification guys on the payroll, and will get rid of them as soon as the
economy turns down. That makes it a very bad career move.
As to the content of his speech, I agree with much of it, but really don't
think of C++ as the holy grail of high-order design languages. What I
think is that FPGAs are going to continue taking market share away from
ASICs, and that verification hassles are a moderately large part of why.
- Dave Chapman
Gold Mountain Sebastopol, CA
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From: Hein van der Wildt <hein=user domain=fenix-da not calm>
Hi John,
An interesting dump of most all available techniques/technologies to deal
with the issue of verification.
But no mention of any pre-verification actions which can and should be
taken at an earlier stage -- such as removing any or all inaccuracies
amongst the lib views, no mention of validation of IP blocks, and no
mention of any validation activity of the QA of the design flow.
I can understand the reluctance of the large EDA players to talk about
this, but the simple removal of silly mismatches and inconsistencies in
the design flow does improve design efficiency by much and avoids all
kinds of delays during design and verification.
During our validation runs we discover so many of these stupid errors,
one wonders why the chip works.
- Hein van der Wildt
Fenix DA Eindhoven, Netherlands
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From: [ Anon #1 ]
Hi John,
Thanks for sending me the Keynote presentation.
Just one comment/question; by not testing the fuctionality that we have
already tested, how can we guarentee that the previously tested funtionality
still works?
- [ Anon #1 ]
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From: Kevin Cameron <edas=user domain=v-ms not calm>
Hi, John,
Wally's talks are always good and usually correct - I would say "on the
money" if he actually knew how to capitalize on his observations, but
Mentor always seems to follow rather than lead.
Basically everything you see happening on a PCB eventually happens on a
chip. In this case he is observing we will transition into building
chips mostly out of pre-verified IP, i.e. if you have to verify it
yourself you will fail because it will take you too long: board-level
designers assume that chips they buy will perform to spec.
The ability to guarantee that an IP block will perform as specified and
not require extensive verification by the end user seems to be beyond
the capabilities of the current CAD tools (and IP suppliers). Maybe
Wally can fix that, but I suspect that the shift in methodology is
beyond that which Mentor, Cadence and Synopsys etc. are capable of,
since it requires admitting that the current tools inadequate.
- Kevin Cameron
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From: [ Anon #2 ]
John, thanks. Any idea what's 'intelligent TB'? He provides some details
during the Q&A - but is he referring to known piece of work?
- [ Anon #2 ]
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From: [ Anon #3 ]
I love that there's no registration required any more. Yes!
- [ Anon #3 ]
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