( ESNUG 473 Item 11 ) ------------------------------------------- [05/29/08]
Subject: Viewer's reactions to the DVcon 08 Troublemaker's Panel video
> This year's Troublemaker's Panel we discussed Mike Santarini, VC's,
> DataQuest, Nvidea, real estate agents, power, US engineering grads,
> 9/11, India, H1-B visas, outsourcing, Cadence, Freescale, NXP,
> bookings bubbles, Verisity Specman, Verilog, P&R, Magma, Sierra,
> data management, Synchronicity, design teams being too large, exit
> strategies, intelligent testbenches, Wally Rhines, ESL, SystemC,
> ANSI C, System Verilog, Matlab, parallel computing, Rajeev Madhavan,
> EDAC, Talus, Magma, Synopsys lawsuit, Atoptech, Broadcom, Sierra,
> Avanti, Mojove, Gerry Hsu, Synopsys Orion, Milkyway, OA, Virtuoso,
> Pcells, PDKs, QuickCap, Silicon Canvas, Dracula, VHDL, FPGAs,
> Mach TA, Adit, AVM, OVM, all-you-can-eat-FAM deals, start-ups,
> Cadence, Mentor, Sierra, Atoptech, ICC, Magma, DFM, ClearShape,
> Invarium, AutoESL, CatapultC, SW discounting, India, Fast SPICE,
> UPF vs. CPF, Ciranova, Pcells, and US kids studying engineering.
>
> See http://www.deepchip.com/videos/trouble08.fhtml
>
> After viewing the debate, feel free to send your reactions. - John
>
> P.S. No registration, no sign up, my videos are now for all to see!
From: Craig Shirley <craig=user domain=apache-da not calm>
Hi John,
I'm looking forward to reviewing this panel!
Fyi, your NVIDIA spelling is incorrect.
- Craig Shirley
Apache Design Automation
---- ---- ---- ---- ---- ---- ----
From: Dick Dowell <dick.dowell=user domain=avagotech not calm>
Hi, John,
Hurray for No Registration! The video worked for me, and I never got it
to work when I had to register! Go figure.
- Dick Dowell
Avago Technoligies
---- ---- ---- ---- ---- ---- ----
From: Dave Chapman <dave=user domain=goldmountain not calm>
Hi, John,
Just watched the first 5 minutes of this panel. Wow. My gut reaction
is "I told you so".
Eight years ago I wrote a paper called "Verilog is Obsolete and We Don't
Have a Good Replacement". It attracted some small amount of attention,
and then nothing.
My basic argument was that Verilog maps to something like 25 gates per
line of source, and that you need a breakthrough in order to not have
the size of chip design teams double every 18 months.
Looks like YOU ARE HERE.
I mean, the team size has been doubling every 18 months and is now well
over 100 people. In 2001 we had maybe 10-20 people on a chip design team.
I told you so.
- Dave Chapman
Gold Mountain Sebastopol, CA
---- ---- ---- ---- ---- ---- ----
From: [ Anon #1 ]
Hi, John,
Who was missing from Cadence?
Who declined to participate? Was a reason given?
I must be anon.
- [ Anon #1 ]
---- ---- ---- ---- ---- ---- ----
From: Steven Gartner <steveg=user domain=cadence not calm>
Hi John,
Who was invited to the panel from Cadence and decided not to show?
- Steve Gartner
Cadence San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Phuong Nguyen <phuong.nguyen=user domain=mindspeed not calm>
Hi, John,
Thank you for an entertaining & informative panel discussion. Having all
those EDA execs sitting on the same panel was quite interesting. They
didn't fight as much this year as they did in the past.
- Phuong Nguyen
Mindspeed Technologies
---- ---- ---- ---- ---- ---- ----
From: Ian Getreu <getreu=user domain=aol not calm>
John,
Was fun. Enjoyed it. Good questions (and answers).
Nice to have no registration - just click and play. Also, good quality.
Good job.
- Ian Getreu
---- ---- ---- ---- ---- ---- ----
From: [ Anon #2 ]
Really enjoyed the video especially having been away from EDA for several
years now. I like no registration!
- [ Anon #2 ]
---- ---- ---- ---- ---- ---- ----
From: [ Anon #3 ]
Hi, John,
1. MAGMA said nothing about Titan and the analog synthesis idea
2. CADENCE absence was disappointing
3. Playing CADENCE was not fun
4. I liked the slick Synopsys answer on ORION - still no real details
5. All backed down from DFM euphoria
6. To the last question none of the participants answered - do we
have more or less opportunities for EE in NA? Exiting is nice
but not the answer to the question. At the beginning was a
little talking about US engineering but at the end they forgot.
Nice initiative, most of them told some real stuff not only marketing
and sales pitch.
Please do it more often. Quality was good for video and sound.
- [ Anon #3 ]
---- ---- ---- ---- ---- ---- ----
From: [ Anon #4 ]
Hi, John,
I really do not appreciate your panelists' comments of the form "If you are
any good, then you'll have no trouble finding a job."
This sort of blame-the-victim crap isn't making you guys any friends.
My inability to find a job in Silicon Vally derives from crooked politicians
who allowed corporate criminals to import Cheap Slave Labor and then throw
out all of the US citizen workers.
Anybody who says different is a liar.
- [ Anon #4 ]
---- ---- ---- ---- ---- ---- ----
From: [ Anon #5 ]
John,
Keep me anon... I watched your video and especially the US kids and
engineering. You only asked the EDA companies about hiring a new grad.
But most of the chip companies hire new grads including us. So please
don't discourage the kids to not go into engineering by questions like
that.
I wish you also asked a question like how many companies sponsor a kid's
education or support a fund to pay for the tuition. Or if there is any
fund to support electrical engineering or for that matter any
engineering or science in general.
- [ Anon #5 ]
Index
Next->Item
|
|
