( ESNUG 473 Item 4 ) -------------------------------------------- [05/29/08]
From: [ Keep Those Cadence Lawyers Away From Me!!! ]
Subject: One analog designer's first look at the Ciranova Virtuoso killer
Hi, John,
Please keep me anonymous.
In my company we have done both manual placement and routing by hand using
Cadence Virtuoso.
We recently evaluated Ciranova's new analog/custom layout tool to automate
the device-level placement of our full custom design. Ciranova took our
SPICE netlist and generated the optimized placement in a Cadence Open Access
database. We did our routing with Virtuoso.
We used Ciranova on an IP block for a TSMC 65 nm shuttle design, earlier
this year. I drove over to the Ciranova office one morning with our netlist
to use their tool onsite, and by the end of the day their app engineer and
I had a final placement.
There were about 40 transistors, of various sizes, in our block. Our final
circuit size: 250 um^2. It took us 4 hours to place the circuit -- which
was 2.5 hours to set up Ciranova's tool, the actual placement took 0.5 hour,
and iteration time was 1 hour.
Following this, it only took about 5 additional hours to route it by hand in
Virtuoso and extracted a post-layout netlist. Oue final circuit passed LVS,
DRC and HSPICE on the first try.
The last design I placed and routed manually using Virtuoso that was this
same size took an entire month! A 2 day total cycle with Ciranova was an
tremendous gain!
Ciranova's tool:
1. Inputs:
- A SPICE netlist and a PCell library. We used PyCells
- A Ciranova tech file. This tech file is a description of the process
design rules and physical design layers, similar to a techfile for
Calibre. It uses a combination of data from the DRC rule deck and
Virtuoso tech file. Creating a new tech file would take a few days,
but Ciranova already had one for TSMC 65.
2. Ciranova automatically optimized our layout for things such as device
abutment, diffusion sharing, and layer merging. Because it incorporated
information from our DRC rules, Ciranova generates layouts that are
design-rule "correct by construction". (Or that's what they claim.)
3. We then added constraints to influence things like hierarchical
composition, matching, symmetry, grouping, and automatic inter-
digitation (which were custom alpha codes by Ciranova). Their signal
flow was implicit in their placement generator. We did our first
placement with no constraints at all, then started adding them and
re-running placement over and over again, adding a couple more
constraints each time until we got a layout I liked.
The entire process took about 10 iterations, and we ended up with 18
constraints total.
We entered the constraints in a textual format. An example is called
"CalCapRow1p" and says: these 3 devices need to be placed side by side,
with their bottom edges aligned.
Name: CalCapRow1p
Type: Row
Param: {Alignment: bottom, XFlip: []}
Contains: [mxcal2p,mxcal3p,mxcal4p]
Interestingly, adding constraints actually made Ciranova's tool run
faster, not slower???
# of Constraints Runtime
----------------------- -----------------
No constraints 5 min 10 sec
10 constraints 2 min 29 sec
18 constraints (final) 28 sec
4. Output
Ciranova outputs the device-level placement in a standard Cadence Open
Access database, which we then imported to our layout tools. (We use
Cadence Virtuoso, Mentor IC-Station, and Tanner L-Edit.)
What's good:
- Run time. I only had to wait a few minutes between each Ciranova run.
- It passed DRC. We didn't have to go back and fix violations by hand
in a layout editor.
- We got Ciranova going fast. Normally Virtuoso takes about 3 weeks of
data preparation before we can start seeing layouts.
- Ciranova passed LVS and our post-layout extracted netlist test-bench;
two of our most important verification steps.
What needs work:
- Ciranova constraints are a text file. Yes, you can get started with
nothing, and the format is sensible. But a big design will have a lot
of constraints; it begs for automation. They've promised a GUI, which
is really needed.
- Ciranova is on Open Access. If your layout flow is already on OA,
great. But if not, you have to transfer the placement via GDSII,
(which is what we did, but then you lose connectivity.) Ciranova
is better if you're already on OA. Sucks if you're not.
- Routing is still manual as always. This is OK, but it would be nice
to at least have some kind of routability metric up front.
One thing I liked about Ciranova is that you can see a lot of different ways
to lay out your circuit. That's consistent with analog design, where often
you don't know what you want until you see what's possible.
- [ Keep Those Cadence Lawyers Away From Me!!! ]
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