( ESNUG 472 Item 9 ) -------------------------------------------- [04/30/08]
Subject: ( ESNUG 469 #6 ) We tested Dafca's ClearBlue on a 65 nm ARM9 CPU
> ClearBlue was very stable - we had no issues there. It instrumented the
> signals that were connected through our main system on the on-chip bus,
> adding 32 kilobytes of memory trace buffer for our instrumented signals.
> We used a dedicated JTAG port to control all the Dafca logic. We tested
> the debug logic directly through this JTAG port and the design was fully
> functional. Our critical path was not affected by the debug logic inside
> and we met our 100 MHz goal for the test chip, with worst case temperature
> and worse case voltage.
>
> We are now promoting our positive experience with it internally in ST.
>
> - Lorenzo Cali
> STMicroelectronics Milan, Italy
From: [ A Foo Fighter ]
Hi, John.
Please keep my name out of this, OK?
We evaluated ClearBlue on a test chip with an ARM9 series CPU, using a 65 nm
process technology. Their debugging interface was a little bit fuzzy at the
time, but since then Dafca has made many improvements to the PTE state
machine designer and significant changes to the group browser GUI and design
navigation capabilities. Also, signal routing is much easier now, as the
groups defined during insertion are carried into analysis tool (available
now but not during the evaluation we did at the beginning of this year).
Our main goal was to monitor all cache signals for the chip -- since we
evaluated ClearBlue on an existing block, we were not assessing its
pre-silicon debug capabilities. For our debug assessment, we hand inserted
errors to see how ClearBlue would handle these instruction/data bugs.
At the time, it took 4 days to bring up and debug our scenarios with
the help of Dafca application engineer.
We see silicon debugging as ClearBlue's biggest strength. Without ClearBlue
we have to find each error one at a time; as we identify and fix each error,
another one appears.
The dual port memory we used is a bit slow for at-speed read operation in
CAPSTM memory to support real-time debugging. However, Dafca claims that
their release in the Q1 of 2008 will use single port memory to improve
speed. There is only a one gate delay for control MUX insertion, but we
did it very carefully for the instrumented RTL synthesis part.
Dafca's instrumentation IP is synthesizable RTL so it does not require any
special libraries. Dafca's IP is treated the same as our functional logic
and mapped to an ordinary standard cell library. Also, Dafca's
instrumentation requires no additional pins as it leverages the existing
JTAG ports for configuration, operation and control.
Based on our eval, we found ClearBlue was helpful with real-time signal
debugging on a working silicon die. ClearBlue is most useful for
complicated SoC designs with smaller nanometer processes, rather than a
relatively small SoC designs.
- [ A Foo Fighter ]
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