( ESNUG 472 Item 8 ) -------------------------------------------- [04/30/08]
Subject: ( ESNUG 454 #18 ) One user's first look at the new EVE Zebu-XXL
> Our largest emulation model utilizes 32 FPGAs or 24 M gates including
> standard logic and SRAMs. This maxes out our ZeBu-XL's capacity. We
> stubbed out some portions of our design to fit into the box.
>
> Several of our designs run with a ZeBu-XL internal clock speed of 1 MHz
> or more. That speed drops into the 800 KHz range when significant amounts
> of data are transfered between the emulation box and an attached PC. At
> these speeds, we are seeing a speedup of 5,000X over SW simulation.
>
> - Mike Dickman
> Palo Alto Semiconductor Santa Clara, CA
From: Helena Krupnova <helena.krupnova=user domain=st not mom>
Hi, John,
We use EVE ZeBu-XXL fast emulator for hardware-software co-verification in
ST's central verification group (FVG). Our team usually handles different
designs from different divisions with different design practices, so our two
most important evaluation criteria were that the emulation system needed to:
1) Compile and map the design into the box automatically.
2) Keep the same fundamental platform speed other FPGA platforms offer.
We used ZeBu for subsystems of 2 SOCs; each were around 5-6 Million gates.
We have an 8 FPGA ZeBu-XXL configuration, so we targeted that capacity when
defining the sub-systems. We were able to have a CPU running at more than
10 MHz on ZeBu for our 5-6 Million gate designs.
We started to use ZeBu in Q2 2006. Our pilot design project was at the RTL
development and integration stage. We targeted a co-emulation platform on
ZeBu to validate the FPGA mapping and the mapping approach. It took us
approximately 2 months to run the first simulations, which included:
1. RTL synthesis.
2. Flow building, or compiling/mapping the netlist produced by RTL synth
into the emulator. This consisted of: design partitioning, pin
multiplexing, clock-tree handling and removal of timing violations,
memory mapping, bus handling, and place and route.
3. Integration with the verification platform and test bench.
For subsequent design iterations the ZeBu related setup portion (excluding
RTL synthesis) only took us about 1 week. We save about 25-30% set up time
with ZeBu time compared to the previous FPGA technology we used.
We use ZeBu in multiple modes:
- HDL acceleration (or co-emulation with an RTL test bench); mainly
useful for validating mapping and possible testbench/RTL changes
done for FPGA.
- In-circuit emulation; main production use mode.
- C++/SystemC transaction-based co-emulation; main production use mode
BEST PARTS:
1. Automatic and semi-automatic partitioning and pin multiplexing. In ZeBu
we can do: an entirely automatic partitioning which is quick but we do
not get the best performance; or a hand partitioning where we manually
fine-tune the partitioning generated by the ZeBu compiler and improve
the performance - this can possibly double the speed.
2. The user does not need to count pins, and the partitioning is always
feasible due to the variable pin multiplexing factor. This lets us
easily map different sub-systems and integrate different IPs, and
allows us to easily respond to the changing needs or priorities of
the verification/SW validation teams.
3. Automatic handling of clock skew/gating problems. It is possible to get
running even a very "dirty" design, before any gated clock/skew cleaning
was done. It is well known that this is the most difficult point for
commercial FPGA platforms. Our own main challenge was cleaning the RTL
for FPGA and making some specific RTL modifications for that purpose.
4. The dynamic probing is great for the initial platform bring-up, as it
lets us see the status of design (clocks, resets, control signals...)
without recompiling. It also lets us have a significant set of signals
for HDL co-emulation without any recompile.
NEEDS WORK:
1. We would like EVE R&D to further improve ZeBu's speed.
2. Our users still need to have a very high expertise in FPGA/prototyping
platforms to get best performance from ZeBu.
3. Integrating FPGA expertise in automatic flow would definitely be useful.
4. We would like to see EVE enhance their automatic partitioning to provide
the same results as with our hand partitioning.
ZeBu-XXL ramps-up rapidly. I would definitely recommend it.
- Helena Krupnova
ST Microelectronics Grenoble, France
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