( ESNUG 472 Item 7 ) -------------------------------------------- [04/30/08]
Subject: ( ESNUG 464 #8 ) We taped out a 65 nm, 2 M instance chip with ETS
> For a 456K instance design with 557K nets:
>
> Cadence ETS non-SI runtime: 15 minutes
> Cadence ETS SI runtime: 3 hours
>
> A plus is the common timing engine (CTE) used for both First Encounter
> and ETS. What this means is that the correlation between the P&R timing
> and signoff timing will be tighter. Also ETS supports ECSM libs so it
> will be possible to do IR-drop using reports from Voltage Storm.
>
> - Jason Perez
> Freescale Semiconductor Austin, TX
From: Umesh Srikantiah <usrikantiah=user domain=sandbridgetech not mom>
Hi John,
We recently taped out a 65 nm wireless design with 2 million instances.
Our Cadence ETS eval was done about 8 months ago and during it, we found
that ETS was within 15 psec of PrimeTime.
For this tape-out, the transition from PrimeTime to ETS was very smooth
and without hitches.
At the block level, our ETS runs on our processor core were 5 minutes
versus around 30 minutes for PrimeTime.
At the full chip level, our ETS run were 50 minutes versus 4 hours on
PrimeTime (on a previous version of our chip).
Support from our Cadence AE was excellent and quickly enabled us to come
up to speed with the tool & scripts.
- Umesh Srikantiah
Sandbridge Technologies Tarrytown, NY
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