( ESNUG 472 Item 2 ) -------------------------------------------- [04/30/08]
Subject: ( SNUG 07 #5 ) We got better area/timing with Incentia DesignCraft
> 2007 - How does Design Compiler rank against its rivals Cadence Get2chip
> RTL Compiler, Ambit, Magma Blast Create, Synplicity ASIC, Incentia
> in your eyes? Which synthesis is your project using now?
>
> Synopsys DC ############################# 67%
> Cadence Ambit # 3%
> Synplify ASIC # 2%
> Cadence Get2chip ########## 22%
> Magma Blast Create ######### 21%
> Incentia # 2%
From: Fei Yan <fyan=user domain=via-telecom not mom>
Hi, John,
I am very surprised if you have not tried TimeCraft and DesignCraft or even
have not heard the name Incentia.
We started using Incentia's DesignCraft synthesis about 5 years ago, about
a year after we used their TimeCraft STA product. Since then we have taped
out 6 designs with DesignCraft.
Before DesignCraft, we used to use Design Compiler. Like with PrimeTime
and TimeCraft, the big difference again was synthesis runtime and gate count
reduction. Design Compiler was so slow that we had to always do bottom up
synthesis (module by module). Each module took an hour up to a few days and
it took about 2 weeks total to have synthesis done using Design Compiler.
When we switched to DesignCraft, synthesizing the whole design took us a
total of only 7 hours.
Also, we've seen DesignCraft's area optimization results (module by module)
range from 8% to 20% better than Design Compiler, with a 10% average area
reduction at the chip level (2 million gates).
For timing results, DesignCraft made our design run faster. Our Teaklite
(DSP) chip used to run at 13 nsec. It's running at 10.8 nsec now.
I am very happy to share my experience with IC designers in using these two
tools. Let me know if you need more information.
- Fei Yan
VIA Telecom San Diego, CA
Index
Next->Item
|
|
