( ESNUG 472 Item 1 ) -------------------------------------------- [04/30/08]

Subject: One user's first impressions of Magma's new Titan Virtuoso-killer

> In this interview, Rajeev announces "Titan", his new Virtuoso-killer,
> along with discussing Pcells, Ciranova, PDKs, Analog Artist, Talus,
> Mojave, QuickCap, the new Quartz-TLX, OA, MatLab, process migration,
> Sagantec, "AnalogWare", Cosmos, Pulsic, fabs, 65 nm, 45 nm, the
> Synopsys-Magma lawsuit, Jay Vleeschhouwer, bean counters, Cadence,
> and Mentor Calibre. 
>
>          See http://www.deepchip.com/videos/titan.fhtml
> 
> After viewing the video, feel free to send in reactions.  :)  - John


From: Ed Hudson <elh=user domain=elcos not mom>

Hi, John,

My company makes microdisplays for large screen high definition TVs.

We used to use Cadence Virtuoso for our AMS design, but we recently decided
to switch to Magma's Titan for 4 reasons:

  - As a small company we get better support from Magma -- especially
    from the Titan group because Magma wants this tool to succeeed.

  - Cadence mixed the tools they now offer and we weren't happy with it.

  - Blast Fusion did really well in a test Verilog-to-polygon design
    we did, so we're betting Titan should do even better.  So far
    that's been true.

  - Our own strategic thinking was that we could greatly influence
    Titan's developement to better serve our own needs.  We have lots
    of internal CAD tools and we'd like them to play nice with with
    Titan.  Purely self interest.  Our long term goal is to dump our
    internal CAD tools because their equivalent functionalty will
    exist in Titan.  Saves on long term support costs for us.

We are using Titan primarily for mixed signal design.  Specifically we're
using FineSim for simulation of our large analog/custom digital blocks and
the Titan Layout Editor and Shape Based Router for the top level assembly.

One of our big main issues is to be able to do the design using only 2 metal
layer routing to save on costs and increase yield.

FineSim: It's fast and accurate.  Our old methodology was to simulate a
block at a time.  (Prior to FineSim, for SPICE we used Silvaco and a public
domain tool called IRsim.)  We were using SPICE only for small cell
functional simulations.  I've used SPICE simulators for over 30 years; for
the first time in my career I've been able to run a 24 million transistor
design, with full SPICE accuracy -- not a switch-level representation, but
with real SPICE!  Our next step will be using it for our IR drop analysis.

The Titan Layout Editor: We were able to load our full chip, all layers
(6 GBytes of GDSII data) into Titan in less than a minute -- all 24 million
transistors worth!!  The tool is very agile.  Panning, zooming, and editing
all occur without any lag time.  We anticipated a few crashes, but so far
the layout editor has surprised us and performed flawlessly (so far.)

Titan Shape Based Router (SBR): We loaded the design within minutes and
were able to complete the top level route, using 2 metal layers only.  I
liked the responsiveness of the tool.  One of the pins at the top was
completely surrounded by metal1/metal2 obstructions.  With its layout
editor, we were able to remove the obstruction and regenerate the abstract
for routing, and the router was then able to complete succesfully.

Things that we would like Titan to improve are:

  - FineSim and Titan (with RC extracts) need to be integrated for
    complete analog simulation environment.  In the past we used
    Dracula and internal stuff.  Right now we're trying to get
    Quartz DRC to work.  We going through the process of trying to
    convert a Calibre deck into a Quartz deck.

  - Titan isn't integrated with our internal block generation software.
    We'll see how well or poorly this goes.  It'll also be a good test
    case of Titan's TCL environment.

  - Although it was promised, Titan (at this point) does NOT do fully
    automated routing of your analog blocks.  It's promised in the
    next release.  We'll see.

John, all of this was from working with a 24 million transistor legacy
design done in a Cadence environment because it's already in silicon and
we know it works.  It's the best vaildation we can do getting started.

As of 3 hours ago, we could run NO DRC's.  Now, with everything converted
it looks like we'll be able to launch a full chip DRC check.  Our thanks to
the Magma Quartz DRC senior AE staff for for getting the Calibre deck
conversion script done on a 4 day notice.  Job well done.

    - Ed Hudson
      Elcos Microdisplays, Inc.                  Sunnyvale, CA
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