( ESNUG 470 Item 10 ) ------------------------------------------- [10/31/07]
From: Maryse Wouters <woutersm=user domain=imec.be>
Subject: We used Synplicity Premier & HAPS-32 to prototype our video chip
Hi, John,
We used Synplicity Premier and the HAPS-32 to prototype our processor on
two Xilinx Virtex-4's. With them we were able to prove feasibility for
our C-programmable reconfigurable architecture and show that the processor
and the corresponding C-compiler were sufficiently stable for use in
portable wireless multimedia devices.
Our chip supports MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions
ranging from QVGA up to D1. The HAPS-32 prototyping board contains two
tightly linked views:
- An processing element array that runs the application data flow.
- A VLIW that executes the control.
Our primary criterion for using Premier was performance. We needed our
product to run real time SVC decoding on a processor prototyped. Premier
was particularly useful in helping us meet our clock frequency target;
we had constrained the FPGA clock input to 50 MHz to decode 30 frames/sec
of H.264/AVC content at CIF resolution.
We originally designed our processor using Synplify Pro for synthesis and
optimization, and Xilinx ISE for P&R. We got 46 MHz, which was good, but
it was critical that we hit 50 MHz, so we used Premier, which bumped our
performance to 52.6 MHz.
It only took us a day to set up the Premier environment. We needed to
modify our input/output timing constraint settings, since they were
different for Premier compared than Synplify-Pro -- initially we used the
wrong timing setting. Once we found the error, it took another day to
make the modification.
Premier's biggest strength is taking the routing delay into account during
placement to achieve timing. In FPGAs, where routing is fixed, you need to
know the routing resources to do a good placement. Therefore ASIC-style
physical synthesis is inaccurate for FPGAs. Graph-based physical synthesis
also cut P&R runtimes significantly.
Premier uses what they call 'graph-based physical synthesis' to represent
the FPGA's pre-existing wires, switches, and placement sites as a detailed
routing resource graph. It automatically outputs timing-correlated legal
placement, and considers the availability of actual FPGA routing resources
when measuring delays, rather than just the physical proximity of instances.
With Premier our design utilization on a Xilinx Virtex4-LX200 was 9% DSP48,
94% memory RAM16, and 43% slices.
The elapsed time was:
- Synplify Pro + Xilinx ISE: 18 hours total (but timing spec was not met)
Synplify Pro (synthesis, optimization): 1 hour
Xilinx ISE (placement and routing) 17 hours
- Synplify Premier + Xilinx ISE: 9 Hours total
Synplify Premier (synthesis, optimization, placement): 3 hours
Xilinx ISE (final placement and routing): 6 hours
Part of the time difference is because ISE does a bad placement, so meeting
the timing with available routing resources takes a long time. Because
Premier does placement in a manner known to meet timing, the design is fully
routable using the Xilinx ISE toolset.
For correlation Premier predicted 51 MHz performance, which was very close
to the actual result of 52.6 MHz.
Premier is now part of our standard tool flow for projects using FPGAs at
90 nm and below, while we continue to use Synplify Pro for Virtex2 FPGAs.
- Maryse Wouters
IMEC Leuven, Belgium
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