( ESNUG 470 Item 9 ) -------------------------------------------- [10/31/07]
From: Chris Tarnovsky <chris=user domain=flylogic.net>
Subject: User benchmark of Mentor Precision RTL Plus vs. its olde version
Hi John,
I have been using Mentor's Precision RTL since 2003 and recently upgraded to
their new "Precision RTL Plus" this month. I measured a 44% improvement in
my Xilinx Spartan 3 FGPA using the RTL "Plus" tool compared to their old
Precision RTL tool. My benchmark data is below.
"Plus" understands better how Xilinx have implemented their architecture vs.
the old Precision RTL. It uses that info to do what they call "physically-
aware synthesis". It makes a big difference when the tool understands the
architecture of the design you are dropping into.
My benchmark method:
- I took exactly same source code, with the same inputs and outputs, and
made one project for 2007 RTL Plus and another for RTL 2006a3.24.
- Everything was automated and executed as a script: Precision compiled
and synthesized the design, then automatically passed it to Xilinx P&R.
This was one time only for each version of Precision; no iterations or
further tweaking.
- I used the same version of Xilinx ISE Foundation 7.1. for P&R. Xilinx
actually has a later version (ISE Foundation 9.1), but it has bugs in
it, so I am sticking with 7.1 for now.
Results:
Precision RTL 2006a3.24 Precision RTL Plus 2007
Performance 57 MHz 82 MHz
Execution time 32 min 32 min
The execution times were 2-3 min of Precision compilation and synthesis with
the rest being Xilinx P&R on an Intel Quad Xeon 5160.
1. The design came in at 90% of a Spartan 3 1500
2. There was no additional setup required for Plus vs. old Precision RTL.
3. Performance numbers are based on Xilinx P&R, not Mentor's own reports.
Because Mentor historically has not had this physical information,
their timing has not been as accurate as Xilinx. Precision RTL tended
to exaggerate the delays over the actual results from Xilinx P&R.
Mentor's timing is getting better, but still Xilinx is the final word.
4. We made the PCB before we designed the logic for this FPGA. The I/Os
had been pin locked (pin constraints), so none of the I/O signals were
allowed to be changed. When I do my reverse engineering projects, I
design and debug at once, so I write the code as tightly optimized as
possible. I didn't notice a difference is Xilinx P&R runtime, just
that the device speed (throughput) was better.
Another interesting stat on the hardware:
Intel Quad Xeon 5160 Quad AMD FX-74
Execution time 32 min 44 min
I initially ran the HW comparison 2 months ago on Precision 2006. Between
the lower speed and the heat that AMD generates, I sold my Quad AMD and just
use Intel Quad Xeon now!
I first started using Mentor in 2001. I used Leonardo at first, and waited
for them to polish Precision before using it. Now I only use Precision.
Precision used to have some significant bugs, but these have been repaired
in the newer version. If a user copied instantiated names, Mentor would
create a long file name that would continue to grow until it exceeded 256
characters and the tool would crash. Mentor had workaround for this, but it
has been fully repaired in the latest version. Xilinx place and route has a
bug that Mentor had a workaround for, where Xilinx had a file name that had
to be deleted if you were using CPLD Xilinx 9500 series. Now Mentor has a
fix for Xilinx's bug directly in Precision.
I would like to see "Plus" become multi-threaded. It automatically does 3-4
takes on a design to find the most optimal result for you. If it could take
advantage of my dual or quad processors, they could spawn 2 or more threads,
one for each optimization, and then let the thread terminate. The runtime
would be cut in half.
Precision has a TcL interface, so I write scripts to automate the process.
"Plus" also has an incremental synthesis approach, where they recompile and
synthesize only the portion of your design affected by a design change.
This can result in a 6x run time savings, but it is mostly relevant more
for very large designs.
- Christopher Tarnovsky
FlyLogic Engineering Vista, CA
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