( ESNUG 470 Item 6 ) -------------------------------------------- [10/31/07]
Subject: ( ESNUG 469 #3 ) User questions whether DC-Topo results are real
> I watched your DAC interview with Gal Hasson on Synopsys DC-Topo and
> wanted to clear up a few misconceptions about Cadence RTL Compiler's
> physical solution. Gal compares it to the "old technology" of Synopsys
> Floorplan Manager, in fact, nothing could be further from the truth.
>
> - Jason Ware
> Cadence Plano, TX
From: [ Doubting Thomas ]
Hi John,
Please keep me anonymous on this one.
I have a question to your ESNUG readers, after looking through the data
available on Deepchip and reading the presentations from the Munich SNUG.
I only (mostly) find eval examples in the ESNUG archives.
Does anyone have a success story with DC-Topo on a real design, with modern
technology and an a chip intended for selling to real customers?
What I am looking for is a DC-Topo success with:
- a design in a 90 or 65 nm process
- above 2 M gates (NAND eq's)
- with multiple RAM's, ROM's,
- multiple voltages (at least IO and Core)
- at least 2 or more IP-blocks from 3rd party vendors.
My reason for this is that everyone at Synopsys keeps telling me how
absolutely fabulous Topo is and how much it can do for my design. I try
and try and try again and again and fail and fail, again and again. I am
using the DC-RM for Topo. I am discussing with my FAE. I am implementing
all the bells and whistles that SNPS R&D are asking for in the synthesis;
and still it fails.
This is on a known good designs (using Cadence Encounter as check) that are
with/without a known good floorplan (DEF), with only one clock system and
the chip has really nice interfaces.
So please tell me I am wrong, that it is possible to use Topo for real
designs and I just have to keep trying to solve my problem. Please give me
a customer tapeout number for DC-Topo! (i.e., no internal tapeouts for weird
research departments. :-) )
- [ Doubting Thomas ]
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