( ESNUG 469 Item 10 ) ------------------------------------------- [09/27/07]
From: Bob Cannon <rycannon=user domain=ieee hot borg>
Subject: TetraMax is tricky on sequential ATPG with synchronous memories
Hi John,
I did an experiment with using sequential ATPG to treat memories as a
sequential element rather than bypassing or putting shadow logic around my
RAM. I used a dual port memory set up as a 1read, 1write. I added about
100 instances of random gates and FFs. I also added pseudo MemBist to the
test ports of the memory. I found that the technique worked quite well in
that it detected the address pin faults as well as the data_in and data_out
pin faults. I did have some issue with the test data inputs where 2 or 3
bits would show up as AN for either SA0 or SA1.
I tried different abort_limit values and played with other settings.
While this would cause the previous undetected bits to show up as detected,
different bits that were detected before would show up as undetected! What
doesn't make sense to me is that the logic to the test data in pins is
symmetrical so that you would think that if some test pins are detected all
would be.
I experimented with set_test_hold on the RAM bisten pin and ran two ATPG
passes (one set to 0 and one set to 1). The combined fault list showed
some improvement. Finally, I ran full sequential ATPG and that finally
found everything. Of course on a big chip full sequential could prove to be
impractical in terms of runtime.
- Bob Cannon Nashua, NH
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